Minimization of noise-induced bit error rate in a high Tc superconducting dc/single flux quantum converter

Ortlepp, Thomas; Toepfer, Hannes; Uhlmann, H.

doi:10.1063/1.1341228

Cited by 11 publications

(4 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recent simulations of the noise-induced bit error rate in HTS digital circuits indicate good chances even for LN 2 temperature operability [17] for suitable circuit technology [18] since connecting Josephson junctions in a circuit results in improved energetic separation of the different switching states as compared to the isolated junction behavior [19].…”

Section: Electronicsmentioning

confidence: 99%

Application Fields of High-Temperature Superconductors

Hott

2004

High Temperature Superconductivity 2

View full text Add to dashboard Cite

Section: Electronicsmentioning

confidence: 99%

Application Fields of High-Temperature Superconductors

Hott

2004

High Temperature Superconductivity 2

View full text Add to dashboard Cite

“…But this approach becomes complicated in the case of multiple junctions [20] and is not applicable for dynamic switching events. We have performed an analytical study to derive error rates of RSFQ modules, and later on this knowledge of rare switching events is used to be considered in the design process [21].…”

Section: Noise Analysis Of the Josephson Junctionmentioning

confidence: 99%

Noise analysis for intrinsic and external shunted Josephson junctions

Ortlepp¹,

Uhlmann²

2004

Supercond. Sci. Technol.

Self Cite

View full text Add to dashboard Cite

In the design of electronic applications (for example, rapid single flux quantum (RSFQ) circuits), the properties of Josephson junctions (JJs) provided by technology are the major requirement. The characteristic voltage I c R n and the dynamic parameter β c are non-negligibly important, but the external shunted junctions are only completely described by including the parasitic inductance between the junction area and the shunt resistor. The first publications of the RSFQ circuit technique were closely followed by many studies on the dynamic influence of this inductance. It has been pointed out that no practical value of this parameter has to be taken into account in the circuit design and optimization process. The operation of RSFQ logic circuits made of high-temperature superconductors (HTS) are strongly influenced by thermal noise. Our paper contains the determination of the digital bit-error rate for all different types of JJs by using a Fokker-Planck equation for describing the influence of thermal fluctuations. Our analysis shows that the parasitic inductance cannot be neglected in terms of noise. The intrinsic shunted junctions like high current density-, SINIS-and all kinds of HTS-JJs provide the best noise immunity for a fixed temperature.

show abstract

“…Our design approach for cells with optimal bit-error rate has been described in detail elsewhere [8,9]. Usually circuits are designed with respect to maximum fabrication yield [10].…”

Section: Development Of Hts Rsfq Cellsmentioning

confidence: 99%

HTS basic RSFQ cells for an optimal bit-error rate

Cassel

Dittmann

Kuhlmann

et al. 2002

Supercond. Sci. Technol.

View full text Add to dashboard Cite

Thermal noise strongly influences the operation of RSFQ (rapid single flux quantum) logic circuits made of high-temperature superconductors (HTS). In the past, the circuit design was based on fabrication yield optimization. A new theoretical study using a method of general determination of the digital bit-error rate (BER) gives hope to develop such devices with a large immunity against noise. With regard to this study the design parameters of a circuit optimized with respect to fabrication yield are far from its minimum bit-error rate. Only for temperatures close to 4 K the parameters determined for fabrication yield match the parameters obtained with BER optimization. For this reason, a new reliable technology for fabrication of HTS circuits is required. We have developed a new fabrication process to serve as a basis for a proof of this new design approach. We have calculated the bit-error rate of a newly designed RSFQ chip with realistic values derived from a test chip which has been fabricated with this new multilayer technology. The new technology contains three superconductor thin films. An inductance smaller than 0.5 pH per square has been reached by using a ground plane.

show abstract

Minimization of noise-induced bit error rate in a high Tc superconducting dc/single flux quantum converter

Abstract: Articles you may be interested inSimulation of sub-k B T bit-energy operation of adiabatic quantum-flux-parametron logic with low bit-error-rate Appl.Temperature dependence of a high-T c single-flux-quantum logic gate up to 50 K

Cited by 11 publications

References 11 publications

Application Fields of High-Temperature Superconductors

Application Fields of High-Temperature Superconductors

Noise analysis for intrinsic and external shunted Josephson junctions

HTS basic RSFQ cells for an optimal bit-error rate

Contact Info

Product

Resources

About