Minimisation of power consumption in digital integrated circuits by reduction of switching activity

An Innovative Design of Low Power Binary Adder based on Switching Activity

“…The design method in [15] furnishes an interesting archive of contemporary techniques of power abstraction and low power motif based on synthesis. The assessment and the switching from 0 → 1 and 1 → 0 at any junction is suggested in [16]. In order to assure the classical probabilistic perspective that restricts the utmost value of SA to one meaning, as presented in [16] was tailored in [17].…”

“…The assessment and the switching from 0 → 1 and 1 → 0 at any junction is suggested in [16]. In order to assure the classical probabilistic perspective that restricts the utmost value of SA to one meaning, as presented in [16] was tailored in [17]. An algorithmic perspective at the logic gate level simplification using Karnaugh maps for minimizing the SA in a combinatorial logic circuit is proposed in [18] and about ten percent reduction in SA at logic gate level is also described in [19].…”

Implementación de máquinas de estado basadas en rom en dispositivos FPGA de xilinx de bajo costo

“…Nombrando como ejemplo un caso específico como lo es la lógica de salida de la máquina, si dentro de la lista de sensibilidad, se nombra el reloj y dentro de la descripción se hace referencia a un flanco del mismo, cada una de las salidas de este proceso será asignada a un Flip-Flop. [12][13][14].…”

Thermal management of 3D integrated circuits with microchannel-based liquid cooling

“…is one such switching activity caused by unbalanced data paths that lead to skew bus switching, another design time approach is to use logic gates with low switching activity through logic manipulation [105][106][107]. It was found that inverter has the greatest switching activity.…”

“…It was found that inverter has the greatest switching activity. Eliminating input inverters were thus proposed in [105,107]. For example, instead of implementing f =x +ȳ + z using inverters and OR gates, it can be implemented as f = xy + z with N AN D gates.…”