Minimal Maximum-Level Programming: Faster memory access via multi-level cell sharing

Berman, Amit; Birk, Yitzhak

doi:10.1109/glocom.2013.6831483

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Cited by 4 publications

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“…In order to do so, the codes constrain the stored levels within a memory block in a way that is most beneficial to the write or read processes. Previous schemes like [1], [2] considered access-optimizing mappings for multi-level cells, but were more limited as they did not use redundancy. In Section II we introduce the first code which is designed for highperformance write.…”

Section: Introductionmentioning

confidence: 99%

Codes for high performance write and read processes in multi-level NVMs

Hemo

Cassuto

2014

2014 IEEE International Symposium on Information Theory

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Multi-level memory cells are used in non-volatile memories in order to increase the storage density. Using multilevel cells, however, imposes higher read and write latencies limiting high speed applications. In this work we study the tradeoff between storage density and write/read performance using codes. The contributions are codes that give high-performance write and read processes with minimal reduction in storage density. We describe the codes, give an analytical treatment of their information rate and speed, and compare them with more basic access schemes and upper bounds.

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Section: Introductionmentioning

confidence: 99%