MIGS: A Multiprocessor Image Generation System Using RISC-like Microprocessors

Anido, M.L.; Allerton, D. J.; Zaluska, Ed

doi:10.1007/978-4-431-68093-2_20

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Floating-point Processing: Leofloat1

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1989

1993

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Cited by 4 publications

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“…LeoFloat combines a 32-bit microcodable floating-point core with concurrent input and output packet communication subsystems (see Figure 4. ), similar to the approach of [3]. The only support chips required are four SRAM chips for external microcode store.…”

Section: Floating-point Processing: Leofloatmentioning

confidence: 99%

Leo

Deering¹,

Nelson²

1993

Proceedings of the 20th Annual Conference on Computer Graphics and Interactive Techniques

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A physically compact, low cost, high performance 3D graphics accelerator is presented. It supports shaded rendering of triangles and antialiased lines into a double-buffered 24-bit true color frame buffer with a 24-bit Z-buffer. Nearly the only chips used besides standard memory parts are 11 ASICs (of four types). Special geometry data reformatting hardware on one ASIC greatly speeds and simplifies the data input pipeline. Floating-point performance is enhanced by another ASIC: a custom graphics microprocessor, with specialized graphics instructions and features. Screen primitive rasterization is carried out in parallel by five drawing ASICs, employing a new partitioning of the back-end rendering task. For typical rendering cases, the only system performance bottleneck is that intrinsically imposed by VRAM.

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Section: Floating-point Processing: Leofloatmentioning

confidence: 99%