Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results

Parès, G.; Minoret, S.; Huet, S.; Lapras, V.; Anciant, R.; Henry, David D.; Sillon, N.; Dunne, B.

doi:10.1109/eptc.2009.5416444

Cited by 12 publications

(7 citation statements)

References 8 publications

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“…Via-middle TSVs require a relatively large (12:1 or higher) aspect ratio [14][15][16]20]. Thus, the width of via-middle TSVs is comparable to the width of via-first TSVs whereas the height is comparable to via-last TSVs.…”

Section: Via-middle Tsvmentioning

confidence: 99%

“…For example, a conformal barrier process is required for the tungsten to adhere to the dielectric in the cavity. A 20 nm titanium nitride (TiN) layer is typically deposited using metal organic chemical vapor deposition (MOCVD) [14]. TiN is a hard, dense, refractory material with sufficiently low electrical resistivity (22 µΩcm) [22].…”

Section: Via-middle Tsvmentioning

confidence: 99%

“…This challenge is partially negated with the use of a tapered TSV structure that progressively shrinks in size [14,15]. This structure is illustrated in Fig.…”

Section: Via-middle Tsvmentioning

confidence: 99%

“…Novel deposition techniques such as atomic layer deposition (ALD) and timemodulated deposition alleviate some of these issues [14,23]. …”

Section: Via-middle Tsvmentioning

confidence: 99%

“…For example, in [12] and [29], via-first TSV technology has been investigated with little attention on circuit design implications. Similarly, via-middle TSVs have been discussed in [14][15][16] focusing primarily on process characteristics. The fabrication constraints of the three TSV technologies are also compared in [30].…”

Section: Previous Workmentioning

confidence: 99%

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Power Distribution in TSV-Based 3-D Processor-Memory Stacks

Satheesh

Salman

2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Electrical Engineering Stony Brook University 2012Three primary techniques for manufacturing through silicon vias (TSVs), viafirst, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this work. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to number of TSVs and decoupling capacitance.iii To my dearest parents, Jayashree Krishnamurthy and Satheesh Lakshminarayana.

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Section: Via-middle Tsvmentioning

confidence: 99%

Section: Via-middle Tsvmentioning

confidence: 99%

“…This challenge is partially negated with the use of a tapered TSV structure that progressively shrinks in size [14,15]. This structure is illustrated in Fig.…”

Section: Via-middle Tsvmentioning

confidence: 99%

“…Novel deposition techniques such as atomic layer deposition (ALD) and timemodulated deposition alleviate some of these issues [14,23]. …”

Section: Via-middle Tsvmentioning

confidence: 99%