Microstructure of interfacial HgTe/CdTe superlattice layers for growth of HgCdTe on CdZnTe (211)B substrates

Wang, Changzhen; Wang, Xiaojin; Zhao, Jun; Chang, Yong; Grein, C. H.; Sivananthan, S.; Smith, David J.

doi:10.1016/j.jcrysgro.2007.09.027

Cited by 9 publications

(2 citation statements)

References 19 publications

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“…All of these applications require high-quality HgCdTe wafers, since the structural defects in the HgCdTe wafers, i.e., cracks, plastic deformation, dislocations, etc., will decrease the resolution of HgCdTe infrared detector focal plane arrays [2]. A large singlecrystalline area of HgCdTe with low damage could be obtained by growing on the CdZnTe substrates [3,4]. On the other hand, it is also obtained by Bridgman method along with the improvement of growth process [5].…”

Section: Introductionmentioning

confidence: 99%

A New High-Efficiency and Low-Damage Polishing Process of HgCdTe Wafer

Wang

Gao

et al. 2012

Materials and Manufacturing Processes

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HgCdTe crystals have been accepted as a very important material of infrared detectors, and due to their soft-brittle nature, machining HgCdTe wafers is a challenge in the field of ultraprecision manufacture. In this article, the new polishing slurry is developed, and the new polishing process is employed to polish HgCdTe wafers; the polishing results showed that the polished surface roughness Ra is as small as 0.32 nm, the polished surface is smooth and flat, and the subsurface damage only contains thin amorphous layer with depth of 3 nm. The material removal mechanism during polishing HgCdTe wafers is that HgCdTe react with oxidant and acid in the polishing slurry, and at last, the polished surfaces are covered with HgCdTe and TeO 2.

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Section: Introductionmentioning

confidence: 99%

A New High-Efficiency and Low-Damage Polishing Process of HgCdTe Wafer

Wang

Gao

et al. 2012

Materials and Manufacturing Processes

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“…To date, the best annealing strategies for CdTe/Si routinely attain the 10 6 cm À2 level, and densities as low as 5 9 10 5 cm À2 have been achieved. 4 Superlattices (SLs) have been observed to block the rise of TDs, reducing the number reaching the free surface in both III-V 5-7 and II-VI [8][9][10][11] semiconductor materials, although their ability to do so varies. In some cases, an SL may even increase the number of dislocations.…”

Section: Introductionmentioning

confidence: 99%

Simulations of Dislocations in CdZnTe/SL/Si Substrates

Ciani

Chung

2009

Journal of Elec Materi

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Discrete dislocation dynamics simulations were employed to study the primary mechanisms by which superlattices (SLs) block threading dislocations (TDs) from reaching the surface of a composite CdZnTe/SL/Si substrate. We found that the difference in strain (composition) across layer boundaries played a key role as to whether a TD might veer away or continue across. We also found that, while the distance between interfaces had little effect on the motion of a single TD, it could have an impact on the dislocation tangle as a whole and should be considered carefully in SL design. We discuss our results in relation to the design of SLs for TD blocking. INTRODUCTIONLattice-matched substrates with large areas are required to obtain economy of scale for the production of high quality long wave infrared (LWIR) Hg 1Àx Cd x Te (MCT) based devices. The best candidate for this task is the composite CdTe/Si substrate; however, high threading dislocation (TD) densities (>10 6 cm À2 ) at the surfaces of CdTe/Si substrates prohibit their effective use for (LWIR) detectors. Johnson et al. 1 showed that R 0 A j (the resistance at zero-bias 9 the junction area) begins to plateau toward its highest value as the etch pit density (EPD) drops below 5 9 10 5 cm À2 . For operation at 78 K, 5 9 10 5 cm À2 is a good target EPD. 2 The achievement of this final device EPD would require the substrate to have an even lower EPD, as the number of TDs increases inside the final MCT layer, 3 even when grown on lattice-matched substrates. To date, the best annealing strategies for CdTe/Si routinely attain the 10 6 cm À2 level, and densities as low as 5 9 10 5 cm À2 have been achieved. 4 Superlattices (SLs) have been observed to block the rise of TDs, reducing the number reaching the free surface in both III-V 5-7 and II-VI 8-11 semiconductor materials, although their ability to do so varies. In some cases, an SL may even increase the number of dislocations. 7 There are a moderate number of adjustable parameters in SL construction, which may not be independent with respect to TD blocking. This leads to a large problem space over which to design and test SLs, while, at the same time, the rules for how each of these parameters might influence dislocation blocking are unclear.In this paper we present results of discrete dislocation dynamics (DDD) 12,13 simulations investigating strategies for dislocation blocking via variable SL periodicities. The number of equations that govern the dislocations, their mutual interactions, and interactions with surfaces and interfaces, is far too large to be tractable by hand. DDD provides a means by which the equations can be integrated numerically and enables SL design parameters to be investigated systematically. Although, by now, the general parameter space for SL layer growth and TD mechanisms are wellunderstood, qualitative rules that govern their intersection still remain largely uncertain. In this work we studied (1) how the individual layer thickness affects the ability of TDs to encounter the next layer, there...

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MCT Superlattices for VLWIR Detectors and Focal Plane Arrays

Garland

2010

Mercury Cadmium Telluride

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Microstructure of interfacial HgTe/CdTe superlattice layers for growth of HgCdTe on CdZnTe (211)B substrates

Cited by 9 publications

References 19 publications

A New High-Efficiency and Low-Damage Polishing Process of HgCdTe Wafer

A New High-Efficiency and Low-Damage Polishing Process of HgCdTe Wafer

Simulations of Dislocations in CdZnTe/SL/Si Substrates

MCT Superlattices for VLWIR Detectors and Focal Plane Arrays

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