Microprocessor Techniques and Construction at the NSLS

Walet

1993

Phys. Rev. C

We study the quantum foundations of a theory of large amplitude collective motion for a Hamiltonian expressed in terms of canonical variables. In previous work the separation into slow and fast (collective and noncollective) variables was carried out without the explicit intervention of the Born-Oppenheimer approach. The addition of the Born-Oppenheimer assumption not only provides support for the results found previously in leading approximation, but also facilitates an extension of the theory to include an approximate description of the fast variables and their interaction with the slow ones. Among other corrections, one encounters the Berry vector and scalar potential. The formalism is illustrated with the aid of some simple examples, where the potentials in question are actually evaluated and where the accuracy of the Born-Oppenheimer approximation is tested. Variational formulations of both Hamiltonian and Lagrangian type are described for the equations of motion for the slow variables. PACS number(s): 21.60.n, 21.60.Ev, 0.3.65.Ca, 03.65.Sq

Section: Generalization Of the Formalism To Include The Effects Of Th...supporting

confidence: 88%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

Quantum theory of large amplitude collective motion and the Born-Oppenheimer method

Walet

1993

Phys. Rev. C

“…The classical aspect has been most fully developed and described in a review [1]. The quantum aspect is presently in a stage of vigorous development [2,3], supplanting the early work on this part of the theory [4,5]. At the same time a program of applications to problems of nuclear structure has been undertaken [6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Classical mappings of the symplectic model and their application to the theory of large-amplitude collective motion

Walet

1994

Phys. Rev. C

We study the algebra Sp(n,R) of the symplectic model, in particular for the cases n=1,2,3, in a new way. Starting from the Poisson-bracket realization we derive a set of partial differential equations for the generators as functions of classical canonical variables. We obtain a solution to these equations that represents the classical limit of a boson mapping of the algebra. We show further that this mapping plays a fundamental role in the collective description of many-fermion systems whose Hamiltonian may be approximated by polynomials in the associated algebra, as is done in the simplest versions of the symplectic model. The relationship to the collective dynamics is formulated as a theorem that associates the mapping with an exact solution of the time-dependent Hartree approximation. This solution determines a decoupled classical symplectic manifold, thus satisfying the criteria that define an exactly solvable model in the theory of large amplitude collective motion. The models thus obtained also provide a test of methods for constructing an approximately decoupled manifold in fully realistic cases. We show that an algorithm developed in one of our earlier works reproduces the main results of the theorem.Typeset using REVT E X * address after Sept.

Magnet Power Supply Control, of the NSLS VUV and X-Ray Storage Rings, Transfer Lines

Ramamoorthy

Singh

et al. 1985

IEEE Trans. Nucl. Sci.

Th« transfar Unas for NSLS VUV and X-ray etorage rlngi have baan apllt. Haw power auppllat have baaa Incorporated with axlitlng ona». Tha existing alcroproc«»«or ayatait haa b««n upgraded In ordar to control tli* additional functions. This system expands tha Input/output port of tha microprocessor to an addressable sarlal/parallal link to asch magntt power supply. Tha implementation of this systsa will be dlacuaaad. IntroductionIn tha past at tha NSLS tha baaa transfar Unas froa tha boos tar rlnf to tha VUV and X-ray ring shsrad common powar auppllas and control. Thay hava baan convartad Co saparata systaaa and aach transfar line haa Its own power supplies and controls. The controla ware developed so that the exiatlng microprocessor systeas could do oore tasks and thus mlnlmlre the demand for additional coaaunlcatlon llnea to the central coapucer ayataa. The control bus to perfora the function Is a parallel multi-drop aystaa. This bus Is an extension of the Input/output ports of the Microprocessor board. The but was lapleaented In two different ways, one to control purchased power supplies and the second for NSLS developed power supplies.The bus Is addressable and Interactive so that whan data and coaaands are sent out, a reply Is sent back to the alcroprocessor. Tha bus Is called P-SUS. Design CoalsThe purpose of a parallel bus (PBUS) Is to link microprocessors to devices or other alcroprocessors. It allows placing device hardware external to the Microprocessor*. Signal processing aodulea such as A/D converters can be placed near the control equipment and minimizes Che distance over which analog signals aust be run. In soae cases the nyaber of devlcea per alcro Is Halted by the nuaber of cards that aay be put In a crate or the nuaber of connectors that can be placed on the rear of a alcro crate. Placing device hardware outside Che alcro overcomes these limitations. It also allows some standardization of hardware.The following definition was proposed as a standard so that all lapleaentationa of a bus would be the aaae. Many different devlcea aay reside on the bus. The only requlreaent Is that each devictt should have Its own address or range of addresses.Tha design requlreaents were:1. It should be very easy to iaplaaant for staple devices.2. It should allow for communications with a saart device such aa another alcro. It Is supposed chst soae device would contain a aicro and have aoae response else limitations such that a handshake would be required.•This work was performed under the auspices of the U.S. Departaent of Energy. Parallel fort BuaMiff**The parallel port bus is based on the standard Intel single board computer 24-blt parallel port. Intel uaes the 8255 parallel port chip on saoy of chair coaputar and peripheral boards. This chip has three S-blt parallel ports which aay be opera»« In several aodas. Tha parallel pore hue uses port A as an 8-blt bidirectional data bua. The SO/Zt coaputar bosrj uaed ac the MIS coaas with bidirectional driver on port A and It If used for Inputtlag or outputting da...