Microcontroller Based Reconfigurable IoT Node

Rajasekaran, C.; Raguvaran, K

doi:10.1109/icfsp.2018.8552060

Cited by 1 publication

(3 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…, H8) with diversified block lengths, regular and irregular, as listed in Table 2, were used for the experimental study. For example, the parity-check matrix of a regular (3,6), (1024, 512) code with submatrix size P = 32 is provided in Figure 5. This matrix, referred to as H1 in Table 2, corresponds to an optimized graph, free of length-4 and length-6 cycles and a minimized number of length-8 cycles.…”

Section: Numerical Resultsmentioning

confidence: 99%

“…The general concept of IoT involves numerous possibilities in which a system's hardware and software can be designed. However, the IoT nodes, which constitute the bottom level of a system, are usually devices containing a set of sensors/actuators and a low-power processor with limited processing capabilities (a microcontroller) (e.g., [2,3]). Machine-tomachine communications over the Internet in an IoT system employ a variety of last-mile communication types, with wired, wireless, or fiber-optic mediums and numerous possible stacks of protocols for the physical layer.…”

Section: Introductionmentioning

confidence: 99%

“…{Base matrix construction}2 If possible (that is, if λ 2 ≥ I/J), insert dual diagonal at the right side of the base matrix W 3. Utilizing the PEG algorithm[20], progressively add edges into the base graph (ones into the remaining part of W), subject to the degree distribution λ.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Efficient LDPC Encoder Design for IoT-Type Devices

et al. 2022

View full text Add to dashboard Cite

Low-density parity-check (LDPC) codes are known to be one of the best error-correction coding (ECC) schemes in terms of correction performance. They have been utilized in many advanced data communication standards for which the codecs are typically implemented in custom integrated circuits (ICs). In this paper, we present a research work that shows that the LDPC coding scheme can also be applied in a system characterized by highly limited computational resources. We present a microcontroller-based application of an efficient LDPC encoding algorithm with efficient usage of memory resources for the code-parity-check matrix and the storage of the results of auxiliary computations. The developed implementation is intended for an IoT-type system, in which a low-complexity network node device encodes messages transmitted to a gateway. We present how the classic Richardson–Urbanke algorithm can be decomposed for the QC-LDPC subclass into cyclic shifts and GF(2) additions, directly corresponding to the CPU instructions. The experimental results show a significant gain in terms of memory usage and decoding timing of the proposed method in comparison with encoding with the direct parity check matrix representation. We also provide experimental comparisons with other known block codes (RS and BCH) showing that the memory requirements are not greater than for standard block codes, while the encoding time is reduced, which enables the energy consumption reduction. At the same time, the error-correction performance gain of LDPC codes is greater than for the mentioned standard block codes.

show abstract

Section: Numerical Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%