Microarchitecture evaluation with physical planning

Abstract

Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the impact of architectural decisions on the physical design, and in particular, the impact on the interconnects. In this paper, we propose MEVA, a system to consider both IPC and cycle time in the design space search for a given microarchitectural design. MEVA can consider a variety of user-specified architectural alternatives that trade IPC and cycle time in the design, and performs accurate floorplanning and simulation to fully evaluate each alternative. The resulting solution will maximize the benefit from both IPC and cycle time to provide a better solution than a design space exploration based simply on IPC or cycle time alone. For a sample architectural design, we are able to search a space of 32 architectural configurations with physical planning in less than 2 hours to find a processor configuration that, in terms of BIPS, outperforms the configuration with the best IPC performance by 14%, and the configuration with the fastest clock by 27%. This initial exploration only considers the boundary cases of a much larger design space, but still features substantial IPC and cycle time variation.

Thermally-Aware Design

“…In addition, the entire design flow of Figure 2.16 may be repeated for several microarchitectural block configurations to identify the optimal configuration. 63 Encyclopedia of Thermal Packaging Downloaded from www.worldscientific.com by MONASH UNIVERSITY on 08/25/15. For personal use only.…”

Wire-driven Microarchitectural Design Space Exploration

“…We applied search pruning to our brute-force method in order to reduce the number of simulations. The simulated annealing approach is based on the algorithm proposed in [2]. For our AMPLE engine, the following constants are used: initial stepping factor α = 0.10, gain threshold = 100, and the stepping size µ = 1.…”

“…Some recent research efforts were attempted and focused on improving the efficiency of the search process with various heuristics [2], [3]. In our AMPLE framework as illustrated in Figure 1, the system first reads the technology parameters, an initial machine description, and the target application benchmark program as input.…”

Interconnect and Thermal-aware Floorplanning for 3D Microprocessors

“…Full chip power modeling including functional units and interconnects is rarely considered. In [4], the performance-meeting requirement was involved during the microarchitecture evaluation. However, the power factor was not considered and an unsuitable set of benchmarks for representing actual microprocessor architecture were used.…”