2016 6th Electronic System-Integration Technology Conference (ESTC) 2016
DOI: 10.1109/estc.2016.7764465
|View full text |Cite
|
Sign up to set email alerts
|

Micro-hybrid system in polymer foil based on adaptive layout

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
3
0

Year Published

2017
2017
2019
2019

Publication Types

Select...
3
2

Relationship

0
5

Authors

Journals

citations
Cited by 5 publications
(3 citation statements)
references
References 2 publications
0
3
0
Order By: Relevance
“…During chips placement step in the pre-defined cavities on the polymer foil, the limited accuracy of the chip placement tool and an unwanted movement of the glued chip on top of the foil in the curing step lead to an offset [10]. The undesirable misalignment and rotation error for each chip, especially for multiple chip integration and interconnection, have detrimental consequences for the metal interconnects, thus calling for a revised layout routing of metal interconnects with far larger process bias.…”
Section: Two-polymer Cfp Technologymentioning
confidence: 99%
See 1 more Smart Citation
“…During chips placement step in the pre-defined cavities on the polymer foil, the limited accuracy of the chip placement tool and an unwanted movement of the glued chip on top of the foil in the curing step lead to an offset [10]. The undesirable misalignment and rotation error for each chip, especially for multiple chip integration and interconnection, have detrimental consequences for the metal interconnects, thus calling for a revised layout routing of metal interconnects with far larger process bias.…”
Section: Two-polymer Cfp Technologymentioning
confidence: 99%
“…This, however, contradicts the CFP concept. The already published adaptive layout technique using a maskless laser writer is proposed as a solution [10].…”
Section: Two-polymer Cfp Technologymentioning
confidence: 99%
“…Circuits are thinned down after fabrication to about 20 µm and are embedded in a polymer package using an innovative adaptive interconnect layout to allow a small wire pitch of below 108 µm on and off chip [14]. The total package is flexible and about 100 µm thick.…”
Section: Thinned Siliconmentioning
confidence: 99%