2009 17th IEEE Symposium on High Performance Interconnects 2009
DOI: 10.1109/hoti.2009.19
|View full text |Cite
|
Sign up to set email alerts
|

MiAMI: Multi-core Aware Processor Affinity for TCP/IP over Multiple Network Interfaces

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
15
0

Year Published

2010
2010
2019
2019

Publication Types

Select...
3
2
2

Relationship

0
7

Authors

Journals

citations
Cited by 21 publications
(15 citation statements)
references
References 17 publications
0
15
0
Order By: Relevance
“…We demonstrated that automatic placement of communicating tasks may significantly help performance [12]. Moreover scheduling and placing processes depending on interrupt affinity and processor topology can reduce the CPU overhead in the context of TCP/IP [6]. We feel that these ideas could be combined in a more general-purpose process placement policy for MPI applications.…”
Section: Discussion and Related Workmentioning
confidence: 99%
“…We demonstrated that automatic placement of communicating tasks may significantly help performance [12]. Moreover scheduling and placing processes depending on interrupt affinity and processor topology can reduce the CPU overhead in the context of TCP/IP [6]. We feel that these ideas could be combined in a more general-purpose process placement policy for MPI applications.…”
Section: Discussion and Related Workmentioning
confidence: 99%
“…Multiple network interfaces can provide high network bandwidth and high availability [24,21,45]. Enforcing CPU affinity for interrupts and network processing has been shown to be beneficial for SMP systems [45] and the same benefits should apply to virtualised multicore systems.…”
Section: Scalability Enhancementmentioning
confidence: 99%
“…Many benchmarking studies suggest that each individual core performs differently across the cores of one multiprocessor [24,32,21]. Veal et al [45] and Hashemian et al [21] observe a CPU single core bottleneck and suggest methods to distribute the bottleneck to achieve better performance.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…Regarding this problem, multirail machines are now commonly considered as a workaround since their multiple NICs scale better with the number of cores. However, such complex architectures, interconnecting numerous hardware components, also raise the need to take affinities and locality into account when scheduling network processing [4].…”
Section: Multicore and Numa Architecturesmentioning
confidence: 99%