MGSim &amp;#x2014; A simulation environment for multi-core research and education

Poss, Raphael; Lankamp, M.; Yang, Qiang; Fu, Jian; Uddin, Imad; Jesshope, Chris

doi:10.1109/samos.2013.6621109

Cited by 11 publications

(7 citation statements)

References 13 publications

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“…The Microgrid project, currently led by researchers at the University of Amsterdam, has different goals, namely to demonstrate how a combination of dataflow scheduling and smart thread management in hardware can accelerate data-parallel compute workloads [20], [21]. However, a by-product of this research is an open source, cycleaccurate simulator of Microgrids of configurable sizes called MGSim [22].…”

Section: Proof-of-conceptmentioning

confidence: 99%

AM : Towards A Hardware Unix Accelerator for Many-Cores

Poss

Koning

2016

IEEE Trans. Parallel Distrib. Syst.

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This article advocates the use of new architectural features commonly found in many-cores to replace the machine model underlying Unix-like operating systems. We present a general Abstract Many-core Machine Model (AM 3), a proof-of-concept implementation and first evaluation results in the context of an emerging many-core, hardware multi-threaded architecture without support for interrupts. Our proposed approach makes it possible to reuse off-the-shelf multithreaded/multiprocess software on massively parallel architectures, without need to change code to use custom programming models like CUDA or OpenCL. Benefits include higher hardware utilization, higher performance and higher energy efficiency for workloads common to general-purpose platforms, such as in datacenters and Clouds. The benefits also include simpler software control over the hardware platform, an enabling factor for the further evolution of parallel programming languages.

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Section: Proof-of-conceptmentioning

confidence: 99%

AM : Towards A Hardware Unix Accelerator for Many-Cores

Poss

Koning

2016

IEEE Trans. Parallel Distrib. Syst.

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“…The SL compiler can generate binary for different implementations of the Microgrid. We have software libraries that provide the run-time systems for the microthreading model on the shared memory SMP machines and referred as svp-ptl [51] and distributed memory for clusters/grids and are referred as Hydra [26] and dsvp-ptl [50] The SL compiler can generate binary for UTLEON3 [9,10], MGSim [5,32] and HLSim [44,45,46,43,47,48,41,42].…”

Section: Sl Tool-chainmentioning

confidence: 99%

Microgrid - The microthreaded many-core architecture

Uddin

2013

Preprint

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Traditional processors use the von Neumann execution model, some other processors in the past have used the dataflow execution model. A combination of von Neuman model and dataflow model is also tried in the past and the resultant model is referred as hybrid dataflow execution model. We describe a hybrid dataflow model known as the microthreading. It provides constructs for creation, synchronization and communication between threads in an intermediate language. The microthreading model is an abstract programming and machine model for many-core architecture. A particular instance of this model is named as the microthreaded architecture or the Microgrid. This architecture implements all the concurrency constructs of the microthreading model in the hardware with the management of these constructs in the hardware.

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“…Every core in the Microgrid supports fine-grained multi-threading and implements the concurrency management of the model in its instruction set architecture (ISA). There exists a cycle-accurate simulator for the Microgrid, named MGSim (Lankamp et al, 2013; Poss et al, 2012, 2013a,b). It simulates all of the low-level details of the architecture and therefore becomes very slow in the execution of large applications.…”

Section: Introductionmentioning

confidence: 99%

One-IPC high-level simulation of microthreaded many-core architectures

Uddin

2016

The International Journal of High Performance Computing Applica

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The microthreaded many-core architecture is comprised of multiple clusters of fine-grained multi-threaded cores. The management of concurrency is supported in the instruction set architecture of the cores and the computational work in application is asynchronously delegated to different clusters of cores, where the cluster is allocated dynamically. Computer architects are always interested in analyzing the complex interaction amongst the dynamically allocated resources. Generally a detailed simulation with a cycle-accurate simulation of the execution time is used. However, the cycle-accurate simulator for the microthreaded architecture executes at the rate of 100,000 instructions per second, divided over the number of simulated cores. This means that the evaluation of a complex application executing on a contemporary multi-core machine can be very slow. To perform efficient design space exploration we present a cosimulation environment, where the detailed execution of instructions in the pipeline of microthreaded cores and the interactions amongst the hardware components are abstracted. We present the evaluation of the high-level simulation framework against the cycle-accurate simulation framework. The results show that the high-level simulator is faster and less complicated than the cycle-accurate simulator but with the cost of losing accuracy.

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MGSim — A simulation environment for multi-core research and education

Cited by 11 publications

References 13 publications

AM : Towards A Hardware Unix Accelerator for Many-Cores

AM : Towards A Hardware Unix Accelerator for Many-Cores

Microgrid - The microthreaded many-core architecture

One-IPC high-level simulation of microthreaded many-core architectures

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