Metrology Challenges for 45 nm Strained-Si Devices

Vartanian, Victor; Sadaka, Mariam; Zollner, Stefan; Thean, Aaron; White, T.; Nguyen, Bich‐Yen; Zavala, M.; McCormick, Larry D.; Prabhu, L.; Eades, D.; Parsons, S.; Collard, H.; Kim, K.; Jiang, Jianhua; Dhandapani, V.; Hildreth, J.; Powers, Robert S.; Spencer, G.; Ramani, N.; Mogab, J.; Kottke, M.; Canonico, M.; Xie, Qiwei; Wang, X.‐D.; Vella, Jarrett H.; Contreras, L.; Theodore, D.; Lu, Bin; Kriske, T.; Gregory, R. B.; Liu, Rendi

doi:10.1063/1.2062965

Cited by 11 publications

(4 citation statements)

References 8 publications

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“…While the transistor threshold voltages are not directly apparent from common RE techniques like delayering and imaging the IC, there are various methods for measuring the channel doping in literature such as, spreading resistance profiling, secondary ion mass spectrometry, scanning capacitance microscopy, kelvin force probing microscopy, and electron holography [11][12][13][14][15]. However, these techniques have limitations in both spatial resolution and accuracy [16][17][18][19]. Even if the available techniques could provide needed resolution and accuracy, probing VT makes the RE process highly sophisticated and more resource intensive.…”

Section: Introductionmentioning

confidence: 99%

Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection

Iyengar

Vontela

Reddy

et al. 2018

Proceedings of the International Symposium on Low Power Electronics and Design

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Due to the ever-increasing threat of Reverse Engineering (RE) of Intellectual Property (IP) for malicious gains, camouflaging of logic gates is becoming very important. In this paper, we present experimental demonstration of transistor threshold voltage-defined switch [2] based camouflaged logic gates that can hide six logic functionalities i.e. NAND, AND, NOR, OR, XOR and XNOR. The proposed gates can be used to design the IP, forcing an adversary to perform brute-force guess-and-verify of the underlying functionality-increasing the RE effort. We propose two flavors of camouflaging, one employing only a pass transistor (NMOS-switch) and the other utilizing a full pass transistor (CMOS-switch). The camouflaged gates are used to design Ring-Oscillators (RO) in ST 65nm technology, one for each functionality, on which we have performed temperature, voltage, and process-variation analysis. We observe that CMOS-switch based camouflaged gate offers a higher performance (~1.5-8X better) than NMOS-switch based gate at an added area cost of only 5%. The proposed gates show functionality till 0.65V. We are also able to reclaim lost performance by dynamically changing the switch gate voltage and show that robust operation can be achieved at lower voltage and under temperature fluctuation.

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Section: Introductionmentioning

confidence: 99%

Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection

Iyengar

Vontela

Reddy

et al. 2018

Proceedings of the International Symposium on Low Power Electronics and Design

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“…The early driving forces included direct measurement of the performances of microelectromechanical system (MEMS) and micro-scale devices and subsequent analysis and prediction of the reliability of these devices [ 1 , 2 ], along with the development of test methods and instruments to determine how the mechanical properties of materials change when their external dimensions or internal characteristic scales are greatly reduced [ 3 , 4 , 5 ]. Over the past two decades, when faced with the dramatic volume shrinkage of microelectronic devices [ 6 , 7 ] and the belief in the tenet for materials that smaller is stronger [ 8 , 9 , 10 ], researchers have made rapid progress in studies of micro- and nanoscale experimental mechanics, including elegant measurement methods with powerful measuring instruments that can be categorized as miniaturized material mechanical testing techniques, MEMS-based and probe-based testing techniques.…”

Section: Introductionmentioning

confidence: 99%

A Multiscale Material Testing System for In Situ Optical and Electron Microscopes and Its Application

Zhiguo

Fang

et al. 2017

Sensors

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We report a novel material testing system (MTS) that uses hierarchical designs for in-situ mechanical characterization of multiscale materials. This MTS is adaptable for use in optical microscopes (OMs) and scanning electron microscopes (SEMs). The system consists of a microscale material testing module (m-MTM) and a nanoscale material testing module (n-MTM). The MTS can measure mechanical properties of materials with characteristic lengths ranging from millimeters to tens of nanometers, while load capacity can vary from several hundred micronewtons to several nanonewtons. The m-MTM is integrated using piezoelectric motors and piezoelectric stacks/tubes to form coarse and fine testing modules, with specimen length from millimeters to several micrometers, and displacement distances of 12 mm with 0.2 µm resolution for coarse level and 8 µm with 1 nm resolution for fine level. The n-MTM is fabricated using microelectromechanical system technology to form active and passive components and realizes material testing for specimen lengths ranging from several hundred micrometers to tens of nanometers. The system’s capabilities are demonstrated by in-situ OM and SEM testing of the system’s performance and mechanical properties measurements of carbon fibers and metallic microwires. In-situ multiscale deformation tests of Bacillus subtilis filaments are also presented.

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“…They can be imaged with high-resolution electron microscopy, but obtaining details of the chemical composition of the structure is now in the realm of counting atoms [5,6].…”

Section: Process Analysismentioning

confidence: 99%

The State-of-the-Art in IC Reverse Engineering

Torrance

James

2009

Lecture Notes in Computer Science

267

132

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Abstract. This paper gives an overview of the place of reverse engineering (RE) in the semiconductor industry, and the techniques used to obtain information from semiconductor products.The continuous drive of Moores law to increase the integration level of silicon chips has presented major challenges to the reverse engineer, obsolescing simple teardowns, and demanding the adoption of new and more sophisticated technology to analyse chips. Hardware encryption embedded in chips adds a whole other level of difficulty to IC analysis. This paper covers product teardowns, and discusses the techniques used for system-level analysis, both hardware and software; circuit extraction, taking the chip down to the transistor level, and working back up through the interconnects to create schematics; and process analysis, looking at how a chip is made, and what it is made of. Examples are also given of each type of RE. The paper concludes with a case study of the analysis of an IC with embedded encryption hardware.

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Metrology Challenges for 45 nm Strained-Si Devices

Cited by 11 publications

References 8 publications

Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection

Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection

A Multiscale Material Testing System for In Situ Optical and Electron Microscopes and Its Application

The State-of-the-Art in IC Reverse Engineering

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