Metrology and Inspection Requirements for Successful Stacking of Integrated Circuits

Abstract

New challenges for wafer metrology solutions have evolved with 3-D integrated circuit (3-D IC) manufacturing technology. The latter allows stacking single chips, electrically connecting them in the vertical direction, and forming a chip structure with significant advantages over traditional chips. However, before 3-D stacking of ICs comes to the mainstream production, numerous metrology issues need to be addressed. The purpose of this paper is to elucidate some of these challenges and also show how some of them can be surmounted. In this paper we discuss the critical in-line metrology needs for successfully stacking ICs.