Methods Used in an Automatic Logic Design Generator (ALERT)

Friedman, T. D.; Yang, Sih-Chin

doi:10.1109/t-c.1969.222727

Cited by 48 publications

(9 citation statements)

References 8 publications

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“…1 2) Early Synthesis: IBM has a long history of contributions to logic synthesis. Beginning in 1953 with Karnaugh Maps [35], through Alert [36], MINI [37], and YLE [38], IBM made progress in easing the task of designing logic. While these methods provided needed improvements, they were all aimed at programmable logic arrays (PLAs)-based and, therefore, suffered from exponential behavior.…”

Section: B Logic Design 1) Timing Analysismentioning

confidence: 99%

EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

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Section: B Logic Design 1) Timing Analysismentioning

confidence: 99%

EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In 1962 Iverson [5] had already shown that APL could be used to describe implementation logic. The Alert system [4], based upon APL, demonstrated that the transformation from an architecture to such an implementation can, in part, be performed in an automated way, and that the resulting implementation can, in turn, be used as the point of departure for the design automation of the realisation. This is of great importance for the design of CAD systems for VLSI design.…”

Section: Description Languagementioning

confidence: 99%

APL: an effective design language

Sinderen

Huijs

Blaauw

1986

IEE Proc. E Comput. Digit. Tech. UK

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The paper describes the use of APL (a programming language) for the specification of a hardware architecture, the description of an initial implementation algorithm, its verification and controlled transformation to a logic design. Because of its power of expression, APL can be used effectively in each of these design domains. The APL interpreter turns any description into an executable prototype. Such a prototype is a powerful tool in the management and execution of a design; it clarifies design choices and assures the logical correctness of the product. This computer-aided-design process, which is illustrated by the design of the front end of a logic analyser, is useful for a variety of design situations, such as LSI/VLSI and computer design.

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“…The DDL work at Wisconsin [Du168,Die71], APDL at Carnegie-Mellon University [Dar69], and ALERT at IBM [Fri68] all began with behavioral specifications and produced technology-independent implementations in the form of boolean equations. The results were usually more expensive than manual implementations and did not take advantage of the target technology.…”

Section: Logic Synthesismentioning

confidence: 99%

A new look at logic synthesis

Darringer

Joyner

1980

Proceedings of the Seventeenth Design Automation Conference on Design Automation - DAC '80

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Despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. Previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization. However, larger scales of integration have made other design requirements and technology restrictions as important as circuit count, and have increased the cost of making an engineering change. Thus it is becoming increasingly important to insure that initial chip designs are correct. This paper outlines an investigation into the feasibility of logic synthesis in this new context. A system is described which will produce a naive implementation automatically from a functional specification, and then will interact with the designer, allowing him to evaluate it with respect to these many factors, and to improve it incrementally by applying local transformations until it is acceptable for manufacture. The use of simple local transformations will insure correct implementations, will isolate technology-specific data, and will allow the total process to be applied to larger VLSI designs. This approach has been tested on the design of a single chip with encouraging results. A prototype synthesis system is now being used to perform further experiments. Logic SynthesisThe goal of logic synthesis is to accept functional specifications for a hardware unit and to generate automatically a detailed, technology-specific implementation comparable in quality to that of an experienced engineer. The nature of this problem depends on the level of the functional description, the set of implementation primitives, and the criteria of acceptability. Initially, we are examining a restricted form of synthesis. That is, we are concentrating on the problem of generating masterslice implementations from low-level register transfer specifications in which all memory elements are Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission. specified. The combinational network between the memory elements must be generated and the entire function must be implemented with primitives from a specified set. Further, the implementation must satisfy given performance requirements and technology restrictions. We hope to determine the feasibility of interactive synthesis in this context, and the applicability of techniques of program analysis and optimization.There has been much work on automating logic design and, although many effective tools have been developed to aid the implementer, synthesis is not considered commercially successful. Early work centered on developing algorithms for translating a boolean function into a minimum two-le...

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Methods Used in an Automatic Logic Design Generator (ALERT)

Cited by 48 publications

References 8 publications

EDA in IBM: past, present, and future

EDA in IBM: past, present, and future

APL: an effective design language

A new look at logic synthesis

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