This paper presents the design of an hybrid coursefine time to digital converter for low power applications. The core of the circuit consists of two current-mode SAR analog to digital converters working in a time-interleaved fashion. The TDC has been fully simulated at the transistor level with a 0.13-µm CMOS technology. The paper discusses the design details and the digital calibration techniques required to achieve a single-shot resolution of about 27 ps while keeping the power consumption below 600 µW.