Metastable States of MLSE Receiver Induced by Extreme PMD Conditions

Abstract

We have measured the performance of a 10Gb/s receiver incorporating maximum-likelihood sequence estimation (MLSE) under conditions of severe polarization-mode dispersion (PMD). We find that certain trajectories of PMD evolution can lead to metastable states of receiver operation. MLSE Receivers for Mitigation of PMDPolarization-mode dispersion (PMD), long recognized as a potential impediment to fiber-optic communication [1,2], has become an issue of immediate importance as 21 st -century data rates meet late 20 th -century fiber plant. To fulfill the need for PMD-tolerant systems operating over long reaches at 10Gb/s, many system builders have turned to receivers incorporating MLSE (maximum-likelihood sequence estimation) circuitry. Such MLSE receivers have been widely studied in simulation, and experimental results for first-order [3-5] and higher-order PMD [6] are becoming available.PMD arises when the two polarization modes supported by an optical fiber become non-degenerate, leading to intersymbol interference as multiple delayed replicas of the signal arrive at the receiver. Although the PMD behavior of deployed fiber is quite complex, for sufficiently narrowbandwidth signals it may be characterized by its first-order component: the differential group delay (DGD) between principal polarization modes [7]. In this paper, we report on a newly discovered phenomenon that can occur when an MLSE receiver is exposed to conditions of extremely high DGD. For DGD ≥1.25 unit interval, changes in the launch state of polarization (SOP) can induce one of two metastable states of operation, states which then persist even after the DGD is reduced to normal operating levels. Below, we discuss the origins, effects, and system implications of these metastable states. Experiments and ResultsIn this paper, a commercial MLSE receiver module from CoreOptics was used in the experiments. The MLSE receiver is composed of a linear optical front end, with a PIN photodetector, and a digital equalizer chip set (DECS) that comprises a 3-bit analog-to-digital converter (ADC), an enhanced clock and data recovery (CDR) circuit and a fourstate Viterbi decoder. Two samples per bit are used (i.e., 2-fold over-sampling) for improved tolerance to clock phase [8].PMD tolerance of the receiver was characterized using the setup shown in Fig. 1. A PRBS payload of length 2 31 -1 was encoded with standard OTU2 FEC into a 10.709 Gb/s bit stream, then combined with a controllable source of ASE noise to create a signal with calibrated OSNR. The DGD source was a JDSU model PE4 first-order PMD emulator, and the launch SOP into it was set with a polarization controller. Pre-FEC bit-error ratio (BER) was extracted from the MLSE receiver, and phase shift of the recovered clock could be measured on the oscilloscope, which was triggered by a clock recovery unit positioned before the DGD source. Since the DGD source is the only polarization-sensitive element in the system, the information about launch SOP can be collapsed into a single variable, the power-splittin...