Metallic contamination in hydrogen plasma immersion ion implantation of silicon

Abstract

In plasma immersion ion implantation ͑PIII͒, ions bombard all surfaces inside the PIII vacuum chamber, especially the negatively pulsed biased sample stage and to a lesser extent the interior of the vacuum chamber. As a result, contaminants sputtered from these exposed surfaces can be reimplanted into or adsorb on the silicon wafer. Using particle-in-cell theoretical simulation, we determine the relative ion doses incident on the top, side, and bottom surfaces of three typical sample chuck configurations: ͑i͒ a bare conducting stage with the entire sample platen and high-voltage feedthrough/supporting rod exposed and under a high voltage, ͑ii͒ a stage with only the sample platen exposed to the plasma but the high-voltage feedthrough protected by an insulating quartz shroud, and ͑iii͒ a bare stage with a silicon extension or guard ring to reduce the number of ions bombarding the side and bottom of the sample platen. Our simulation results reveal that the ratio of the incident dose impacting the top of the sample platen to that impacting the side and bottom of the sample stage can be improved to 49% using a guard ring. To corroborate our theoretical results, we experimentally determine the amounts of metallic contaminants on 100 mm silicon wafers implanted using a bare chuck and with a 150 mm silicon wafer inserted between the 100 mm wafer and sample stage to imitate the guard ring. We also discuss the effectiveness of a replaceable all-silicon liner inside the vacuum chamber to address the second source of contamination, that from the interior wall of the vacuum chamber. Our results indicate a significant improvement when an all-silicon liner and silicon guard ring are used simultaneously.

Semiconductor applications of plasma immersion ion implantation

“…As the required hydrogen dose for the layer transfer process is quite high, typically in the mid 10 16 atoms cm −2 , PIII is a more economical alternative than conventional beam-line ion implantation. In addition to innovations in hardware, the success of PIII stems from intensive research and development on the uniformity of ion dose and implant energy as well as on other concomitant processing issues such as contamination [41][42][43].…”

Control of implantation area in direct-current plasma immersion ion implantation (DC-PIII)

“…2(c) and 2(d) to 2(a) and 2(b), flatter contours are observed when the sample stage is closer to the grid. We can also change the potential contours by using different sample stage geometry, for instance, by increasing the dimension of the wafer holder using a guard-ring [18] and adopting a beveled edge on the bottom of the sample chuck [19].…”

“…Although the situation is improved, some of the ions are still implanted into the edge of the stage or supporting rod. Such phenomena are undesirable because of the introduction of sputtered contamination [18]. Therefore, to accomplish 100% top surface implantation and control the implantation area, a proper relationship among the radius of the wafer stage , radius of the grid , and distance between the grid to the top of the stage is necessary.…”