Metal-Al₂O₃-GaN capacitors with an ultraviolet/ozone plasma-treated interface

Abstract

In this study, interface quality of p-type GaN metal-oxide-semiconductor capacitors (n-MOSCAPs) improved with the interface oxide layer (Ga 2 O x ) formed by ultraviolet/ozone (UV/O 3 ) treatment. X-ray photoelectron spectroscopy, transmission electron microscopy, and X-ray dispersive spectroscopy were employed to investigate the Ga 2 O x interface layer which reduced trapped charge density (Q ot ) and interface trap density (D it ) of n-MOSCAPs. The thickness of the Ga 2 O x layer was found to be ∼1 nm. From the frequency-dispersion capacitance-voltage measurements, the Q ot averaged over the GaN bandgap decreased from 9.40 × 10 11 to 7.77 × 10 11 cm −2 eV −1 and the D it near the valence band edge decreased from 9.78 × 10 12 to 6.27 × 10 12 cm −2 eV −1 . The method to improve the interface quality could be applied to enhancement in the performance of p-GaN electronic devices such as MOS field-effect transistors and high-electron mobility transistors. © 2020 The Japan Society of Applied Physics which combines with molecular O 2 and generates ozone O 3 . Then, the 254 nm UV photons dissociate ozone O 3 and form molecular oxygen O 2 and singlet atomic oxygen 1 O 2 ( 1 Δ g ), which is 94.29 kJ mol −1 (0.98 eV) higher in energy than the triplet ground state of

Investigation on the interface trap characteristics in a p-channel GaN MOSFET through temperature-dependent subthreshold slope analysis

“…Table 1 summarizes the reported D it values at the Al 2 O 3 /p-GaN interface [22,[29][30][31]. The D it in this work are comparable to the reported ones at the Al 2 O 3 /p-GaN interface [22,[29][30][31], and obviously higher than those at the Al 2 O 3 /n-GaN interface [32,33].…”

Study of an Al2O3/GaN Interface for Normally Off MOS-Channel High-Electron-Mobility Transistors Using XPS Characterization: The Impact of Wet Surface Treatment on Threshold Voltage VTH

“…Higher threshold voltages were previously reported in the literature with decreasing GaO x interfacial layer thickness for ALD-Al 2 O 3 /n-GaN MOS capacitors and MOCVD-Al 2 O 3 MOS-HEMTs, attributed to ionized donor levels at the Al 2 O 3 /GaO x interface . On the other hand, Kim et al reported good interfacial properties using UV/O 3 treatment, showing that an ultrathin good-quality Ga-oxide layer can be beneficial . Therefore, we can expect a higher threshold voltage for an MOSc-HEMT by either further decreasing Ga oxidation or by controlling the properties of the Ga-oxide interfacial layer .…”

“…31 On the other hand, Kim et al reported good interfacial properties using UV/O 3 treatment, showing that an ultrathin good-quality Ga-oxide layer can be beneficial. 32 Therefore, we can expect a higher threshold voltage for an MOSc-HEMT by either further decreasing Ga oxidation or by controlling the properties of the Ga-oxide interfacial layer. 33 Since the Ga oxidation is higher for etched samples than as-epi samples (see Figure 4), we can conclude that the etching-induced damage has a detrimental impact on the threshold voltage.…”

Passivation of hole traps in SiO2/GaN metal-oxide-semiconductor devices by high-density magnesium doping

“…On the other hand, as for the forward sweeps of the low and medium samples, both the maximum capacitance and the gate voltage showed a discrepancy between the experimental and ideal values that became pronounced depending on the doping conditions, suggesting a change in the density and energy distribution of hole traps near the interface. On the basis of these findings and previous reports, [19][20][21][22][23][24][25][26] it can be concluded that rather than the UHPA process, 27) the concentration of Mg atoms and/or the Fermi level of the p-GaN substrate play a decisive role in the passivation of hole traps.…”

“…17,18) In contrast, there are few reports on p-type GaN MOS capacitors that had well-behaved capacitance-voltage (C-V ) characteristics. [19][20][21][22][23][24] Because of the significant number of hole traps located near the oxide/GaN interfaces, a large C-V hysteresis is usually observed for p-type MOS capacitors. 25) Even worse, the surface potential of GaN is pinned and an ideal amount of hole accumulation at the MOS interface hardly occurs regardless of the gate dielectric materials used.…”