Message Dispatch on Pipelined Processors

Abstract

Abstract. Object-oriented systems must implement message dispatch efficiently in order not to penalize the object-oriented programming style. We characterize the performance of most previously published dispatch techniques for both statically-and dynamically-typed languages with both single and multiple inheritance. Hardware organization (in particular, branch latency and superscalar instruction issue) significantly impacts dispatch performance. For example, inline caching may outperform C++-style "vtables" on deeply pipelined processors even though it executes more instructions per dispatch. We also show that adding support for dynamic typing or multiple inheritance does not significantly impact dispatch speed for most techniques, especially on superscalar machines. Instruction space overhead (calling sequences) can exceed the space cost of data structures (dispatch tables), so that minimal table size may not imply minimal run-time space usage.

A general framework for inheritance management and method dispatch in object-oriented languages

“…We give a very brief summary of the dispatch techniques. For detailed descriptions, see [Dri93], and for a comparison of relative dispatch performance, see [DHV95].…”

“…Note that during dispatch, indirections may incur a penalty beyond just the operation itself due to load latency (in pipelined processors, the result of a load started in cycle i is not available until cycle i+L). In the analysis of [DHV95], it is assumed that the load latency, L, is 2 (non-pipelined processors can assume L = 1). This implies that each extra indirection incurred by the DTF algorithms will slow down dispatch by at least one cycle (for the load itself) and by at most L cycles (if there are not other operations that can be performed while waiting for the load).…”

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“…Inlining [2,10], method devirtualisation [13] and techniques for the efficient implementation of message dispatch [11] have been extensively researched.…”

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“…However, modern pipelined processors execute the additional o set adjustment instruction during the delay time required for branching to the method's code [11]. So, surprisingly, multiple inheritance overheads are negligible even in the presence of polymorphic variables.…”