Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances

Abstract

International audienceIn this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network. Unlike previous clustered mesh architectures, the mesh of tree allows us to consider large clusters sizes (thanks to MFPGA depopulated local interconnect). Experimentation shows that we obtain a reduction of 14% in switches number and 2 times in the placement and routing run time. Furthermore, compared to MFPGA, the mesh of tree achieves full mutability of all MCNC benchmarks since we can easily control both clusters LUTs occupation and mesh channel width

Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and Technologies

“…5. The optimization program uses the router program implemented using the pathfinder algorithm [10,18,20], which uses an iterative, negotiation-based approach to successfully route all nets in an application netlist. The router program in association with a binary search algorithm, considers the same architecture with different p values at each levels of the two-tier 3D Tree-based FPGA to determine the smallest number of input and output signals at each Tree levels by allowing to route the benchmark circuits.…”

“…The interconnect delay of Treebased architecture increases exponentially [10,14,18] as the Tree grows to higher levels. Horizontal partitioning methodology is introduced optimize the exponential rise in Tree network delay as the Tree grows to higher levels.…”

“…3 [12,18], in a Tree-based FPGA the reduction in number of inputs/outputs of the clusters at level impacts the number of routing resources at level + 1, since the number of DMSBs/UMSBs at level + 1 is equal to the number of inputs/outputs at level . At first, the optimization program considers architecture break-point level with different Rent (p) values.…”

“…The impact of cluster size and LUT (Look-Up- Table) size on area is been presented in [10,18]. The experimental data analysis shows Tree-based FPGA architecture with cluster arity equals 4 and LUT size equal 4 is the best in terms area and speed [10,18].…”

OTIS-MOT: an efficient interconnection network for parallel processing

“…MOT has been shown as an efficient interconnection network for single-chip parallel processing by Balkan [3][4][5]. It has also been studied for FPGA [27] and MFPGA [28] architectures by Marrakchi et al This network can provide logarithmic time algorithms for many problems such as matrix-vector multiplication, sorting, packet routing, prefix computation, minimum spanning trees, convex hull and so on [16,22,30]. Algorithms for other computations, including image compression, broadcasting and gossiping and Euclidean distance [1,21,37], have been efficiently developed on this architecture.…”