MERIC and RADAR Generator: Tools for Energy Evaluation and Runtime Tuning of HPC Applications

Vysocky, Ondrej; Beseda, Martin; Řı́ha, Lubomı́r; Zapletal, Jan; Lysaght, Michael; Kannan, Venkatesh

doi:10.1007/978-3-319-97136-0_11

Cited by 6 publications

(11 citation statements)

References 13 publications

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“…Tiwari et al [7] proposed DVFS strategy be used both intra-node and inter-node to reduce power consumption by the CPU. Vysocky et al [8] introduced tools, and applied them to CPU to save energy by tuning hardware parameters during the runtime.…”

Section: Related Workmentioning

confidence: 99%

“…For each configuration, the previously trained models ((4) and ( 6)) are used to predict its normalized energy consumption (5) and speedup (7). Once the predictions for all memory configurations are available (8), the dominant points are calculated and returned as predicted a Pareto set (9). Note that the feature oversampling technique does not affect the prediction phase, but is only applied to features in the training data.…”

Section: Overviewmentioning

confidence: 99%

“…Code benchmarks are generated by pattern: each pattern covers a specific feature, and generates a number codes with different instruction intensities (as a consequence, each pattern is designed to stress a particular component of the GPUs). For instance, the pattern b-int-add includes nine codes with a variable number of integer addition instructions, from 2 0 to 2 8 . This training code design enables a good coverage of (the static part of) the feature space.…”

Section: Training Datamentioning

confidence: 99%

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Accurate Energy and Performance Prediction for Frequency-Scaled GPU Kernels

2020

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Energy optimization is an increasingly important aspect of today’s high-performance computing applications. In particular, dynamic voltage and frequency scaling (DVFS) has become a widely adopted solution to balance performance and energy consumption, and hardware vendors provide management libraries that allow the programmer to change both memory and core frequencies manually to minimize energy consumption while maximizing performance. This article focuses on modeling the energy consumption and speedup of GPU applications while using different frequency configurations. The task is not straightforward, because of the large set of possible and uniformly distributed configurations and because of the multi-objective nature of the problem, which minimizes energy consumption and maximizes performance. This article proposes a machine learning-based method to predict the best core and memory frequency configurations on GPUs for an input OpenCL kernel. The method is based on two models for speedup and normalized energy predictions over the default frequency configuration. Those are later combined into a multi-objective approach that predicts a Pareto-set of frequency configurations. Results show that our approach is very accurate at predicting extema and the Pareto set, and finds frequency configurations that dominate the default configuration in either energy or performance.

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Section: Related Workmentioning

confidence: 99%

Section: Overviewmentioning

confidence: 99%

Section: Training Datamentioning

confidence: 99%

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Accurate Energy and Performance Prediction for Frequency-Scaled GPU Kernels

2020

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“…On the other side, when measuring a single processor efficiency, there is not an easy way to interpose a power meter between the CPU and the motherboard. To tackle this issue, given the increasing interest towards processors power monitoring and the involvement of developers communities in optimizing the energy efficiency of applications [4,5], recent processor chip designs have embedded power meters to monitor energy consumption or power drain while running applications codes.…”

Section: Introductionmentioning

confidence: 99%

ThunderX2 Performance and Energy-Efficiency for HPC Workloads

et al. 2020

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In the last years, the energy efficiency of HPC systems is increasingly becoming of paramount importance for environmental, technical, and economical reasons. Several projects have investigated the use of different processors and accelerators in the quest of building systems able to achieve high energy efficiency levels for data centers and HPC installations. In this context, Arm CPU architecture has received a lot of attention given its wide use in low-power and energy-limited applications, but server grade processors have appeared on the market just recently. In this study, we targeted the Marvell ThunderX2, one of the latest Arm-based processors developed to fit the requirements of high performance computing applications. Our interest is mainly focused on the assessment in the context of large HPC installations, and thus we evaluated both computing performance and energy efficiency, using the ERT benchmark and two HPC production ready applications. We finally compared the results with other processors commonly used in large parallel systems and highlight the characteristics of applications which could benefit from the ThunderX2 architecture, in terms of both computing performance and energy efficiency. Pursuing this aim, we also describe how ERT has been modified and optimized for ThunderX2, and how to monitor power drain while running applications on this processor.

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“…Indeed, energy consumption is relevant in computer engineering research to find the roadmap for a sustainable development of the next generation of large scale computing platforms. Number of tools have been developed to tackle the problem at several levels, from the system level [6], to the resource manager [7] and the runtime execution such as: triggering the clock frequency at runtime accordingly to the specific case (i.e., lowering the frequency if memory bound) [8] and performing fine-grained power measurements that enable energy-aware performance optimizations [9]. However, a significant improvement in term of energy efficiency is still much related to algorithms and software engineering.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Performance and Energy Assessment of a Lattice Boltzmann Method Based Application on the Skylake Processor

Girotto¹,

Schifano

Calore

et al. 2020

Computation

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This paper presents the performance analysis for both the computing performance and the energy efficiency of a Lattice Boltzmann Method (LBM) based application, used to simulate three-dimensional multicomponent turbulent systems on massively parallel architectures for high-performance computing. Extending results reported in previous works, the analysis is meant to demonstrate the impact of using optimized data layouts designed for LBM based applications on high-end computer platforms. A particular focus is given to the Intel Skylake processor and to compare the target architecture with other models of the Intel processor family. We introduce the main motivations of the presented work as well as the relevance of its scientific application. We analyse the measured performances of the implemented data layouts on the Skylake processor while scaling the number of threads per socket. We compare the results obtained on several CPU generations of the Intel processor family and we make an analysis of energy efficiency on the Skylake processor compared with the Intel Xeon Phi processor, finally adding our interpretation of the presented results.

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MERIC and RADAR Generator: Tools for Energy Evaluation and Runtime Tuning of HPC Applications

Cited by 6 publications

References 13 publications

Accurate Energy and Performance Prediction for Frequency-Scaled GPU Kernels

Accurate Energy and Performance Prediction for Frequency-Scaled GPU Kernels

ThunderX2 Performance and Energy-Efficiency for HPC Workloads

Performance and Energy Assessment of a Lattice Boltzmann Method Based Application on the Skylake Processor

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