Memristor-Based Edge Computing of Blaze Block for Image Recognition

Ran, Huanhuan; Wen, Shiping; Li, Qian; Yang, Yin; Shi, Kaibo; Feng, Yuming; Zhou, Pan; Huang, Tingwen

doi:10.1109/tnnls.2020.3045029

Cited by 15 publications

(5 citation statements)

References 33 publications

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“…Figures 2 and 3 shows the internal view of the IFG memory [11]. By taking the above two models as a reference including some modifications in them, a compact IFG model characterized in Verilog-A code is developed, and importing this Verilog-A code file to cadence generates the IFG model [12]. The cadence model is shown in Figure 4.…”

Section: Memristor-based Ifg Modelmentioning

confidence: 99%

Investigation of Memristor-Based Neural Networks on Pattern Recognition

Routhu,

Phalguni Singh,

Raja

et al. 2023

Hmam2

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Section: Memristor-based Ifg Modelmentioning

confidence: 99%

Investigation of Memristor-Based Neural Networks on Pattern Recognition

Routhu,

Phalguni Singh,

Raja

et al. 2023

Hmam2

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“…Image recognition on the edge computing nodes is a critical network challenge for the current Internet. Ran et al [86] develop a memristor-based blaze block circuit for edge computing system with a specific focus on image recognition. The design includes a memristive convolutional neural network followed by multiple modules of memristive pooling and block elements for the operation.…”

Section: Image Recognition Architecturementioning

confidence: 99%

“…Power efficient match line design [64] Power consumption model [63] Energy footprint for future architectures [62] Switching characteristics [29] Combinational switching traits [30] Cognitive properties [31][32] Three terminal memristors [33] Electrical properties [34][35] Power efficiency traits [36] Gate array architectures [75] Reconfiguration architectures [76] Novel FPGA architectures [77] Pattern classification [81] Anomaly detection [82][83] Real-time data analysis [84] Feature extraction [85] Image recognition [86]…”

Section: Memristive Tcammentioning

confidence: 99%

On Memristors for Enabling Energy Efficient and Enhanced Cognitive Network Functions

Saleh

Koldehofe

2022

IEEE Access

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The high performance requirements of nowadays computer networks are limiting their ability to support important requirements of the future. Two important properties essential in assuring cost-efficient computer networks and supporting new challenging network scenarios are operating energy efficient and supporting cognitive computational models. These requirements are hard to fulfill without challenging the current architecture behind network packet processing elements such as routers and switches. Notably, these are currently dominated by the use of traditional transistor-based components. In this article, we contribute with an in-depth analysis of alternative architectural design decisions to improve the energy footprint and computational capabilities of future network packet processors by shifting from transistor-based components to a novel component named Memristor. A memristor is a computational component characterized by non-volatile operations on a physical state, mostly represented in form of (electrical) resistance. Its state can be read or altered by input signals, e.g. electrical pulses, where the future state always depends on the past state. Unlike in traditional von Neumann architectures, the principles behind memristors impose that memory operations and computations are inherently colocated. In combination with the non-volatility, this allows to build memristors at nanoscale size and significantly reduce the energy consumption. At the same time, memristors appear to be highly suitable to model cognitive functionality due to the state dependence transitions in the memristor. In cognitive architectures, our survey contributes to the study of memristorbased Ternary Content Addressable Memory (TCAM) used for storage of cognitive rules inside packet processors. Moreover, we analyze the memristor-based novel cognitive computational architectures built upon self-learning capabilities by harnessing from non-volatility and state-based response of memristors (including reconfigurable architectures, reservoir computation architectures, neural network architectures and neuromorphic computing architectures).

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“…Note that, as the numbers of antennas and UEs increase, the complexity of these basic matrix operations cannot be ignored and can even become dominant. As an example, in the field of machine learning, memristive neural network circuits are considered one of the potential paths to the future of artificial intelligence due to their ability to perform basic matrix operations with significantly lower energy consumption and area compared to conventional complementary metal oxide semiconductor (CMOS) circuits [22]- [24]. In [25], a memristor-based synaptic circuit was used for online gradient descent training.…”

Section: Introductionmentioning

confidence: 99%

Low-Complexity Tomlinson-Harashima Precoding Update Algorithm for Massive MIMO System

Fang,

Chen,

Chen

et al. 2024

IEEE Trans. Commun.

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Efficient implementation of Tomlinson-Harashima precoding (THP) is crucial in massive multiple-input-multipleoutput (MIMO) systems with a large number of antennas at the base station (BS) serving many user equipments (UEs). To address the high computational complexity of THP, in this paper, we first propose novel THP update algorithms that can avoid recomputing the THP filters when a new UE arrives or departs. Specifically, by using the Gram-Schmidt process and a series of Givens matrices, the THP filters are computed without full matrix operations. Then we extend the THP update algorithms to a more general scenario when multiple multi-antenna UEs arrive or depart. In this case, the proposed algorithms use both direct and iterative approaches. Moreover, the computational complexity of the proposed algorithms is derived and compared with that of the conventional THP. Finally, to further align with the practical scenario, we analyze and derive the approximate closeform expressions for the sum achievable rate of the proposed algorithms under imperfect channel state information (CSI). Simulation results are provided to illustrate the effectiveness of the proposed algorithms. The impact of quasi-static fading and slow time-varying scenarios with imperfect CSI on the communication performance of the proposed algorithms is also evaluated.

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Memristor-Based Edge Computing of Blaze Block for Image Recognition

Cited by 15 publications

References 33 publications

Investigation of Memristor-Based Neural Networks on Pattern Recognition

Investigation of Memristor-Based Neural Networks on Pattern Recognition

On Memristors for Enabling Energy Efficient and Enhanced Cognitive Network Functions

Low-Complexity Tomlinson-Harashima Precoding Update Algorithm for Massive MIMO System

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