Memristive Sisyphus circuit for clock signal generation

Pershin, Yuriy V.; Shevchenko, S. N.; Nori, Franco

doi:10.1038/srep26155

Cited by 10 publications

(9 citation statements)

References 31 publications

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“…The introduction of resistive switching (RS) devices (also called memristors) to the set of standard electronic components is expected to enrich significantly the landscape of modern circuit design and development [1][2][3][4][5]. The memristor has been known as the fourth fundamental circuit element ever since Leon Chua postulated its existence in 1971 [6].…”

Section: Introductionmentioning

confidence: 99%

Exploring the “resistance change per energy unit” as universal performance parameter for resistive switching devices

Gomez

Vourkas

Abusleme

et al. 2020

Solid-State Electronics

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Resistive switching (RS) device (memristor) technology is continuously maturing towards industrial establishment. There are RS devices that demonstrate an "incremental" (analog) switching behavior, whereas others change their state in a binary form. The final achieved resistance is generally a function of the applied pulse characteristics, i.e. amplitude and duration. However, variability-both from device to device but also from cycle to cycle-and the stochastic nature of internal RS phenomena, still hold back any universal tuning approach based solely on these two magnitudes, making also difficult the qualitative comparison between devices with different material compounds owing to the SET/RESET voltages being dependent on the biasing conditions. In this work we demonstrate experimentally using commercial RS devices from Knowm Inc. that the switching energy is not very sensitive to the biasing conditions. We explored experimentally the SET-RESET behavior of bipolar RS devices from the energy point of view. We figured out the quantitative effect of the injected energy to the resistive state of the devices, and proposed an analytical model to explain our observations in the energy consumption during the switching process. Our results lay the foundations for the definition of "resistance change per energy unit" as a performance parameter for this emerging device technology.

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Section: Introductionmentioning

confidence: 99%

Exploring the “resistance change per energy unit” as universal performance parameter for resistive switching devices

Gomez

Vourkas

Abusleme

et al. 2020

Solid-State Electronics

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“…The paper differs from existing papers in the literature where the memristor oscillators use ideal, abstract, or artificial memristor models, that cannot accurately describe the behavior of real memristor devices implemented in nanotechnology [24]. The approach in the manuscript to implement an oscillator is also basically different from the quoted papers in the literature [7], [37], [39] where the oscillations are built upon the hysteresis loops displayed by the memristor in the v − i plane. In that case, the memristor is not a programmable nonlinear resistor, rather the state variable undergoes wide variations during the transient oscillations.…”

Section: Introductionmentioning

confidence: 84%

“…Similarly, [38] investigated the nonlinear dynamics and bifurcations in a modified Shinriki oscillatory circuit also using a Knowm memristor. We also mention the article [39] that reports on the design and experimental realization of a memristive frequency generator with digital logic gates, a single-supply voltage and a threshold-type non-volatile memristive device.…”

Section: Introductionmentioning

confidence: 99%

Oscillatory Circuits With a Real Non-Volatile Stanford Memristor Model

et al. 2022

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Stanford memristor model is a widely used model that accurately characterizes real nonvolatile metal-oxide resistive random access memory (RRAM) devices with bipolar switching characteristics. The paper studies for the first time the dynamics and bifurcations in a class of nonlinear oscillators with real non-volatile memristor devices obeying Stanford model. This is in contrast with papers in the literature considering oscillators with ideal, abstract, or artificial memristor models, that are unable to describe physical memristors implemented in nanotechnology. One main new idea in the paper is to use the memristor as a programmable nonlinear resistor. Namely, two principal modes of operation are considered. 1) Analogue transient phase: the oscillator is designed so that in the transient oscillations the voltage on the memristor is below threshold, hence the main memristor state variable, i.e., the gap of the insulating material, is almost constant and the memristor behaves as a static nonlinear resistor. 2) Programming phase: the nonlinear characteristic of the memristor, which depends on the gap, can be changed via the application of voltages above threshold. The paper studies nonlinear oscillations in the transient phase for a fixed gap as well as the bifurcations phenomena displayed when the gap is varied. The paper also discusses the differences between the approach in the paper and those to design other memristor oscillators with nonvolatile memristors.INDEX TERMS Bifurcations, Chua's circuit, complex dynamics, memristor, Stanford model.

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“…Fortunately, some reported memristor-based artificial neural networks have shown that these developments may become feasible in the near future, at least in relatively small scale (Alibart and Zamanidoost, 2013; Garbin et al, 2014; Prezioso et al, 2015). With the development of integration techniques for large scale memristor crossbar or even 3D networks (Yu et al, 2013; Li et al, 2016), as well as memristor for logical or arithmetical computations (Borghetti et al, 2010; Gale, 2015) to reduce complex peripheral circuits by replacing the digital neurons, we envisage a real chip able to perform interesting memory tasks.…”

Section: Discussionmentioning

confidence: 99%

Hierarchical Chunking of Sequential Memory on Neuromorphic Architecture with Reduced Synaptic Plasticity

Deng

Wang

et al. 2016

Front. Comput. Neurosci.

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Chunking refers to a phenomenon whereby individuals group items together when performing a memory task to improve the performance of sequential memory. In this work, we build a bio-plausible hierarchical chunking of sequential memory (HCSM) model to explain why such improvement happens. We address this issue by linking hierarchical chunking with synaptic plasticity and neuromorphic engineering. We uncover that a chunking mechanism reduces the requirements of synaptic plasticity since it allows applying synapses with narrow dynamic range and low precision to perform a memory task. We validate a hardware version of the model through simulation, based on measured memristor behavior with narrow dynamic range in neuromorphic circuits, which reveals how chunking works and what role it plays in encoding sequential memory. Our work deepens the understanding of sequential memory and enables incorporating it for the investigation of the brain-inspired computing on neuromorphic architecture.

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Memristive Sisyphus circuit for clock signal generation

Cited by 10 publications

References 31 publications

Exploring the “resistance change per energy unit” as universal performance parameter for resistive switching devices

Exploring the “resistance change per energy unit” as universal performance parameter for resistive switching devices

Oscillatory Circuits With a Real Non-Volatile Stanford Memristor Model

Hierarchical Chunking of Sequential Memory on Neuromorphic Architecture with Reduced Synaptic Plasticity

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