Memristive Non-Idealities: Is there any Practical Implications for Designing Neural Network Chips?

Krestinskaya, Olga; Irmanova, Aidana; James, Alex Pappachen

doi:10.1109/iscas.2019.8702245

Cited by 34 publications

(18 citation statements)

References 15 publications

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“…Several nonidealities cause the deterioration of the performance of memristive crossbar-based neural net architectures. Figure 1 shows some nonidealities such as a limited number of stable resistive states, [36][37][38] conductance variation, [39][40][41] memristor aging issues, [21] endurance, [34,42] reliability issues, [43] and device failure. [35] Limiting the number of stable resistive state leads to low precision of dot product multiplication, which, in turn, reduces the memristive neural network accuracy.…”

Section: Memristor and Memristor Nonidealitiesmentioning

confidence: 99%

Automating Analogue AI Chip Design with Genetic Search

Krestinskaya

Salama

James

2020

Advanced Intelligent Systems

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Optimization of analogue neural circuit designs is one of the most challenging, complicated, time‐consuming, and expensive tasks. Design automation of analogue neuromemristive chips is made difficult by the need to design chips at low cost, ease of scaling, high‐energy efficiency, and small on‐chip area. The rapid progress in edge AI computing applications generates high demand for developing smart sensors. The integration of high‐density analogue computing AI chips as coprocessing units to sensors is gaining popularity. This article proposes a hardware–software codesign framework to speed up and automate the design of analogue neuromemristive chips. This work uses genetic algorithms with objective functions that take into account hardware nonidealities such as limited precision of devices, the device‐to‐device variability, and device failures. The optimized neural architectures and hyperparameters successfully map with the library of relevant neuromemristive analogue hardware blocks. The results demonstrate the advantage of proposed automation to speed up the analogue circuit design of large‐scale neuromemristive networks and reduce overall design costs for AI chips.

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Section: Memristor and Memristor Nonidealitiesmentioning

confidence: 99%

Automating Analogue AI Chip Design with Genetic Search

Krestinskaya

Salama

James

2020

Advanced Intelligent Systems

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“…This makes the use of memristor as an analog memory in large crossbar array not practical, however, as a discrete state device and as a binary state device, they can be used effectively, in small arrays. The crossbar also suffers from sneak path problems, parasitic resistors, and wire resistors, that can further limit the large scaling of crossbar that can be implemented today [61,54].…”

Section: Crossbar Arraysmentioning

confidence: 99%

An overview of memristive cryptography

James

2019

Eur. Phys. J. Spec. Top.

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Smaller, smarter and faster edge devices in the Internet of things era demands secure data analysis and transmission under resource constraints of hardware architecture. Lightweight cryptography on edge hardware is an emerging topic that is essential to ensure data security in near-sensor computing systems such as mobiles, drones, smart cameras and wearables. In this article, the current state of memristive cryptography is placed in context of lightweight hardware cryptography. The paper provides a brief overview of the traditional hardware lightweight cryptography and cryptanalysis approaches. The contrast for memristive cryptography with respect to traditional approaches is evident through this article, and need to develop a more concrete approach to developing memristive cryptanalysis to test memristive cryptographic approaches is highlighted. a

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“…The binarization operation transforms full-precision weights into binary values using the signum function, described in Eq. (1).…”

Section: A Binary Weight Regularizationmentioning

confidence: 99%

“…ReRAM devices, in such configurations, can be used to reduce the time complexity of 2D matrix-vector multiplications, used extensively during forward and backward propagation cycles in DNNs, from O(n 2 ) to O(n), and in extreme cases to O(1). However, current ReRAM crossbars face concerns of aging, non-idealities and endurance [1], that limit the accuracy of their conductive states, affecting the reliability and robustness of memristive DNNs.…”

Section: Introductionmentioning

confidence: 99%

Variation-aware Binarized Memristive Networks

Lammie

Krestinskaya

James³

et al. 2019

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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The quantization of weights to binary states in Deep Neural Networks (DNNs) can replace resource-hungry multiply accumulate operations with simple accumulations. Such Binarized Neural Networks (BNNs) exhibit greatly reduced resource and power requirements. In addition, memristors have been shown as promising synaptic weight elements in DNNs. In this paper, we propose and simulate novel Binarized Memristive Convolutional Neural Network (BMCNN) architectures employing hybrid weight and parameter representations. We train the proposed architectures offline and then map the trained parameters to our binarized memristive devices for inference. To take into account the variations in memristive devices, and to study their effect on the performance, we introduce variations in RON and ROFF. Moreover, we introduce means to mitigate the adverse effect of memristive variations in our proposed networks. Finally, we benchmark our BMCNNs and variationaware BMCNNs using the MNIST dataset.

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Memristive Non-Idealities: Is there any Practical Implications for Designing Neural Network Chips?

Cited by 34 publications

References 15 publications

Automating Analogue AI Chip Design with Genetic Search

Automating Analogue AI Chip Design with Genetic Search

An overview of memristive cryptography

Variation-aware Binarized Memristive Networks

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