Memory Window Ratio Enhancement of p-Type WSe₂ Memtransistors Using Dielectric GeSe₂ Nanosheets with Asymmetric Interfaces for Neuromorphic Computing

Abstract

The emergence of 2D wide-bandgap semiconductor (WBGS) GeSe 2 as charge-trapping dielectrics has helped realize superior devices by using an extremely simple device setup. However, the controllability of deep-gap-state defects in 2D GeSe 2 poses a challenge due to the vulnerability and susceptibility of charge-trapping centers, resulting in various problems, i.e., small memory window and poor device durability during programming. Herein, we deliberately perform asymmetric interfacial oxidation to reinforce the memory performance based on the WSe 2 /Janus-GeSe 2 van der Waals heterostructure, which exhibits a giant memory window ratio of 88.5% (70.8 V at ±40 V gate sweep range), high-room-temperature hole mobility of 15 cm 2 V −1 s −1 , and low nonlinearity factor close to 0 with regard to synaptic weight update characteristics. The information storage performance is excellent, owing to the interface rendered by asymmetric oxidation in the GeSe 2 layer, providing an effective charge-trapping layer and atomically flat surface to enhance the mobility of the WSe 2 channel. The controllable strategy helps to derive a simple design principle to realize high-performance 2D WBGS GeSe 2 -based memory and electrical synaptic devices with complex neural functions.