Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores

Saeed, Ahsan; Dasari, Dakshina; Ziegenbein, Dirk; Rajasekaran, Varun; Rehm, Falk; Pressler, Michael; Hamann, Arne; Mueller-Gritschneder, Daniel; Gerstlauer, Andreas; Schlichtmann, Ulf

doi:10.1109/rtas54340.2022.00019

Cited by 9 publications

(11 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As shown, for short regulation periods ( 32 μs), MemGuard is affected by extremely high overhead-up to 2.4 slowdown ratio. These effects are in-line with previous studies (Yun et al 2016;Saeed et al 2022) that have shown around 10% overheads for periods of around 100 μs.…”

Section: Interrupt Overheadssupporting

confidence: 93%

“…Implementation on Linux on the Xilinx Zynq UltraScale+ ZCU102 (Xilinx 2024b). Results are in line with other work (Yun et al 2016;Saeed et al 2022) and extended beyond 100 µs MemGuard. Precisely accounting for this interference is complex, resulting in pessimistic worst-case bandwidth thresholds.…”

Section: Inherent Pessimismsupporting

confidence: 91%

“…Memory bandwidth is monitored using performance counters. Depending on platforms capabilities, implementations of MemGuard have used PMCs from cores' PMUs (Yun et al 2016;Schwaericke et al 2021) or from the DRAM memory controller (Sohal et al 2020;Saeed et al 2022). Since overutilization of memory controllers is detrimental to predictability (Sohal et al 2020), hard realtime systems dimension the memory budget allowed for regulated cores using the principle of maximum sustainable bandwidth.…”

Section: Background and Motivationmentioning

confidence: 99%

“…MemGuard relies on the capabilities of the PMU to deliver a regulation interrupt to a core upon budget depletion. When such an interrupt is received, the core idles by either scheduling a CPU-intensive high-priority task (Yun et al 2016;Saeed et al 2022), or by stalling the core at the hypervisor level (Sohal et al 2020;Schwaericke et al 2021). One timer interrupt periodically replenishes the budget and possibly unblocks the regulated core.…”

Section: Background and Motivationmentioning

confidence: 99%

“…This contrasts with the wide range of performance metrics exported by modern platforms at multiple levels of their complex memory hierarchy-e.g. at the level of PE (ARM 2016a; Xilinx 2024b), interconnect (ARM 2016b), and memory controller (Sohal et al 2020;Saeed et al 2022). Third, it forces to integrate additional system-level software components at the OS (Yun et al 2013) or hypervisor level (Modica et al 2018;Sohal et al 2020), with the corresponding engineering and performance overheads.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

Zuepke,

Bastoni,

Chen

et al. 2024

Real-Time Syst

View full text Add to dashboard Cite

In today’s multiprocessor systems-on-a-chip, the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time analysis. Memory regulation via throttling is one of the most practical techniques to mitigate interference. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and conduct an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite.

show abstract

Section: Interrupt Overheadssupporting

confidence: 93%

Section: Inherent Pessimismsupporting

confidence: 91%

Section: Background and Motivationmentioning

confidence: 99%

Section: Background and Motivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

Zuepke,

Bastoni,

Chen

et al. 2024

Real-Time Syst

View full text Add to dashboard Cite

show abstract

Pattern-Based Information Flow Control for Safety-Critical On-Chip Systems

Dörr,

Schade,

Becker

2023

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Mcti: mixed-criticality task-based isolation

Hoornaert,

Ghaemi,

Bastoni

et al. 2024

Real-Time Syst

View full text Add to dashboard Cite

The ever-increasing demand for high performance in the time-critical, low-power embedded domain drives the adoption of powerful but unpredictable, heterogeneous Systems-on-Chip. On these platforms, the main source of unpredictability—the shared memory subsystem—has been widely studied, and several approaches to mitigate undesired effects have been proposed over the years. Among them, performance-counter-based regulation methods have proved particularly successful. Unfortunately, such regulation methods require precise knowledge of each task’s memory consumption and cannot be extended to isolate mixed-criticality tasks running on the same core as the regulation budget is shared. Moreover, the desirable combination of these methodologies with well-known time-isolation techniques—such as server-based reservations—is still an uncharted territory and lacks a precise characterization of possible benefits and limitations. Recognizing the importance of such consolidation for designing predictable real-time systems, we introduce MCTI (Mixed-Criticality Task-based Isolation) as a first initial step in this direction. MCTI is a hardware/software co-design architecture that aims to improve both CPU and memory isolations among tasks with different criticalities even when they share the same CPU. In order to ascertain the correct behavior and distill the benefits of MCTI, we implemented and tested the proposed prototype architecture on a widely available off-the-shelf platform. The evaluation of our prototype shows that (1) MCTI helps shield critical tasks from concurrent non-critical tasks sharing the same memory budget, with only a limited increase in response time being observed, and (2) critical tasks running under memory stress exhibit an average response time close to that achieved when running without memory stress.

show abstract

Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores

Cited by 9 publications

References 22 publications

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

Pattern-Based Information Flow Control for Safety-Critical On-Chip Systems

Mcti: mixed-criticality task-based isolation

Contact Info

Product

Resources

About