Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures

Srikanth, Sriseshan; Rabbat, Paul G.; Hein, Eric R.; Deng, Bobin; Conte, Thomas M.; DeBenedictis, Erik P.; Cook, Jeanine; Frank, Michael P.

doi:10.1109/hpca.2018.00065

Cited by 7 publications

(3 citation statements)

References 111 publications

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“…It can be avoided by carefully selecting the workload and employing advanced residue interaction methods [30]. Moreover, recent research in computer architecture verifies that, including memory hierarchy, all computer parts can efficiently run within the RNS format [35].…”

Section: High-precision Integrated Photonic Calculationmentioning

confidence: 99%

Integrated photonics modular arithmetic processor

Wu,

Guo

et al. 2023

Preprint

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Integrated photonics computing has emerged as a promising approach to overcome the limitations of electronic processors in the post-Moore era, capitalizing on the superiority of photonic systems. However, present integrated photonics computing systems face challenges in achieving high-precision calculations, consequently limiting their potential applications, and their heavy reliance on analog-to-digital (AD) and digital-to-analog (DA) conversion interfaces undermines their performance. Here we propose an innovative photonic computing architecture featuring scalable calculation precision and a novel photonic conversion interface. By leveraging Residue Number System (RNS) theory, the high-precision calculation is decomposed into multiple low-precision modular arithmetic operations executed through optical phase manipulation. Those operations directly interact with the digital system via our proposed optical digital-to-phase converter (ODPC) and phase-to-digital converter (OPDC). Through experimental demonstrations, we showcase a calculation precision of 9 bits and verify the feasibility of the ODPC/OPDC photonic interface. This approach paves the path towards liberating photonic computing from the constraints imposed by limited precision and AD/DA converters.

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Section: High-precision Integrated Photonic Calculationmentioning

confidence: 99%

Integrated photonics modular arithmetic processor

Wu,

Guo

et al. 2023

Preprint

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“…For example, it is known that the Residue Number System (RNS) [32] can help distribute contiguous data to a wider range [25,26,73]. Such a hash function would be computed by concatenating the set of residues (moduli) R(κ) of key κ against a pre-determined set of co-prime bases B such that R(κ) = {κ%b, b ∈ B}.…”

Section: Tree Partitioningmentioning

confidence: 99%

MetaStrider

Srikanth

Jain

Lennon

et al. 2019

ACM Trans. Archit. Code Optim.

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Reduction is an operation performed on the values of two or more key-value pairs that share the same key. Reduction of sparse data streams finds application in a wide variety of domains such as data and graph analytics, cybersecurity, machine learning, and HPC applications. However, these applications exhibit low locality of reference, rendering traditional architectures and data representations inefficient. This article presents MetaStrider, a significant algorithmic and architectural enhancement to the state-of-the-art, SuperStrider. Furthermore, these enhancements enable a variety of parallel, memory-centric architectures that we propose, resulting in demonstrated performance that scales near-linearly with available memory-level parallelism.

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“…Although operating entirely on RRNS data and literals avoids the significant overheads of converting to/from binary, representing a memory address (for the purposes of Program Counter (PC), Load (LD), and Store (ST)) in an RRNS format naively may cause significant degradation in locality and changes memory access patterns, which is fundamental to memory systems performance. This issue has already been handled by Srikanth et al [70], where they propose bit-manipulation techniques as well as a compiler based approach, with little to no overhead. Of the techniques proposed, their rns_sub scheme, which essentially subtracts the least significant residue from the others, renders the most energy-efficient architecture along with the added advantage of requiring no support from the software stack.…”

Section: Creepy Overviewmentioning

confidence: 99%

Extending Moore’s Law via Computationally Error-Tolerant Computing

Deng

Srikanth

Hein

et al. 2018

ACM Trans. Archit. Code Optim.

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Dennard scaling has ended. Lowering the voltage supply (V dd) to sub-volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, it is possible to correct the occasional errors caused due to lower V dd in an efficient manner and effectively lower power. By deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and energy savings realized by permitting lower V dd. One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling computational error correction at a fraction of an overhead compared to conventional approaches. We use the RRNS scheme to design a Computationally-Redundant, Energy-Efficient core, including the microarchitecture, Instruction Set Architecture (ISA) and RRNS centered algorithms. From This paper is an extension of "Computationally-Redundant Energy-Efficient Processing for Y'all (CREEPY)" [11]. This submission adds the following: (1) Correction factor analysis for RRNS signed arithmetic, including an improved correction factor computation for signed multiplication via an LUT based mechanism. (Section 4.8.5) (2) Design and evaluation of an efficient RRNS multiplier unit by using the index-sum technique, along with associated re-derivation of suitable RRNS bases. (Sections 4.4 and 4.5) (3) A novel adaptive check insertion strategy that leverages hardware/software runtime or compiler. (Section 4.6.3) (4) Impact of multi-domain voltage supply to further lower energy consumption. (Sections 4.7, 6.1 and 6.3) (5) Improved evaluation accuracy by simulating an LLC-main memory hierarchy instead of a perfect cache. (Section 5) (6) Energy limit analysis for binary, RNS and RRNS cores. (Section 6) These add significantly more than 30% new material and provide greater insight into RRNS core design. W.r.t. written content, every section has been revamped to better present the new findings above.

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Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures

Cited by 7 publications

References 111 publications

Integrated photonics modular arithmetic processor

Integrated photonics modular arithmetic processor

MetaStrider

Extending Moore’s Law via Computationally Error-Tolerant Computing

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