Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture

Abstract

Modern computing applications require more and more data to be processed. Unfortunately, the trend in memory technologies does not scale as fast as the computing performances, leading to the so called memory wall. New architectures are currently explored to solve this issue, for both embedded and off-chip memories. Recent techniques that bringing computing as close as possible to the memory array such as, In-Memory Computing (IMC), Near-Memory Computing (NMC), Processing-In-Memory (PIM), allow to reduce the cost of data movement between computing cores and memories. For embedded computing, In-Memory Computing scheme presents advantageous computing and energy gains for certain class of applications. However, current solutions are not scaling to large size memories and high amount of data to compute. In this paper, we propose a new methodology to tile a SRAM/IMC based architecture and scale the memory requirements according to an application set. By using a high level LLVM-based simulation platform, we extract IMC memory requirements for a certain class of applications. Then, we detail the physical and performance costs of tiling SRAM instances. By exploring multi-tile SRAM Place&Route in 28nm FD-SOI, we explore the respective performance, energy and cost of memory interconnect. As a result, we obtain a detailed wire cost model in order to explore memory sizing trade-offs. To achieve a large capacity IMC memory, by splitting the memory in multiple sub-tiles, we can achieve lower energy (up to 78% gain) and faster (up to 49% gain) IMC tile compared to a single large IMC memory instance.

Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing

“…In this case, several memory instances with a limited word length (e.g. 32-or 64-bit) can be used to reach the targeted data vector length, while sharing the same digital wrapper to limit area and leakage power penalties [8]. A similar partionning can be done to overcome the limitation of the number of words per SRAM instance, as shown in Fig.…”

Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator

“…General-purpose code compilers such as gcc and clang can be used to program IMC architectures through macros, like [9] for example. The problem is that this solution shows limited expressiveness and code portability, as such a dedicated solution for IMC would be preferable.…”

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization

“…By using a memory partitioning into smaller tiles, the Tile Address Mapper allows to scale the architecture with some limits: energy cost of individual accesses is inversely proportional to the read access time. In terms of physical design, the Tile Address Mapper provides an energy/performance trade-off as long as the number of tiles is limited [9].…”

“…Regarding the physical scalability of the multi-tile memory architecture, we have evaluated the wiring cost and the correct trade-off between C-SRAM tile size and tile performance. As presented in [9], a wiring cost and energy model based on Place&Route shows the scalability of multiple SRAM tiles: for a 256 kB of total memory size, composing an 4×16 array of 4 kB tile, the wiring cost between tiles is about 50% in read access time, while partitioning in array allows to save massive dynamic power. The C-SRAM architecture 67.20 * * SRAM memory access in one instruction.…”