Memory Reliability Model for Accumulated and Clustered Soft Errors

Lee, Soon-Young; Baeg, Sanghyeon; Reviriego, Pedro

doi:10.1109/tns.2011.2164555

Cited by 11 publications

(4 citation statements)

References 19 publications

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“…With increasing integration density, the probability of multi-bit upsets (MBU) also increases [16]. A comparison of the scaling trend of Q crit between the 6T and 8T SRAM bit cell is shown in Fig.…”

Section: Sram Errors Due To Particle Strikes (Q Crit )mentioning

confidence: 99%

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

Herkersdorf

Engel

Glaß

et al. 2020

Dependable Embedded Systems

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The Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technologies at the semiconductor material or device levels. RAP assumes that each of such physical faults will eventually manifest as a single- or multi-bit binary signal inversion or out-of-specification delay in a signal transition between bit values. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, finite state machine (FSM) states, IP macro-interfaces, or software variables. Thus, design concerns can be investigated at higher abstraction layers without the necessity to further consider the full details of lower levels of design. This chapter introduces the ideas of RAP based on examples of particle strike, noise and voltage drop induced bit errors in SRAM cells. Furthermore, we show by different examples how probabilistic bit flips are systematically abstracted and propagated towards instruction and data vulnerability at MPSoC architecture level, and how RAP can be applied for dynamic testing and application-level optimizations in an autonomous robot scenario.

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Section: Sram Errors Due To Particle Strikes (Q Crit )mentioning

confidence: 99%

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

Herkersdorf

Engel

Glaß

et al. 2020

Dependable Embedded Systems

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show abstract

“…For example, the failure probability of one SRAM cell depends on the error state of neighboring SRAM cells due to the probability of Multi Bit Upset (MCU) [8]. For an 8T SRAM cell it also depends on the stored value of the SRAM cell as the bit flip probability of a stored one is different from a stored zero.…”

Section: Correlated (Error) States Smentioning

confidence: 99%

“…45"nm" 65"nm" 90"nm" Figure 5: Conditional probabilities for multiple upsets dependent on the first single event upset for different technologies [16,8]. Multi Bit Upsets we therefore have to add error state variables to the model.…”

Section: Condiandonal)probability)mentioning

confidence: 99%

“…For this we first have to characterize the occurrence probability of given shapes [15]. Using these occurrence probabilities we can account for Multi Bit Upsets using conditional probabilities which determine the probability that an adjacent cell is upset given the upset of spatially close cells [8]. Figure 5 shows the conditional probabilities of having n additional upsets given a erroneous bit in an SRAM cell array due to MBU for different technologies.…”

Section: Condiandonal)probability)mentioning

confidence: 99%

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Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Herkersdorf

Aliee

Engel

et al. 2014

Microelectronics Reliability

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The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods. AbstractThe Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.

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ISS: An Iterative Scrubbing Strategy for Improving Memory Reliability Against MBU

Wang

2016

Human Centered Computing

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Memory Reliability Model for Accumulated and Clustered Soft Errors

Cited by 11 publications

References 19 publications

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

ISS: An Iterative Scrubbing Strategy for Improving Memory Reliability Against MBU

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