2006 International Conference on Field Programmable Logic and Applications 2006
DOI: 10.1109/fpl.2006.311241
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Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures

Abstract: Configurable architectures offer the unique opportunity of customizing the storage allocation to meet specific applications' needs. In this paper we describe a compiler approach to map the arrays of a loop-based computation to internal memories of a configurable architecture with the objective of minimizing the overall execution time. We present an algorithm that considers the data access patterns of the arrays along the critical path of the computation as well as the available storage and memory bandwidth. We… Show more

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Cited by 6 publications
(3 citation statements)
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References 9 publications
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“…Get an estimate of clock-period: clk_rd_est := Lat(1, t); 4. cost := (lIt (tempL2)I1 t) * l * clkprd_est;5. For each false dependency di E A do a. DRVi := 1; b.…”
mentioning
confidence: 99%
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“…Get an estimate of clock-period: clk_rd_est := Lat(1, t); 4. cost := (lIt (tempL2)I1 t) * l * clkprd_est;5. For each false dependency di E A do a. DRVi := 1; b.…”
mentioning
confidence: 99%
“…et al[5] presents a custom array mapping approach for generalized configurable We have used Xilinx Virtex 11[7] FPGA architecture for performing our experiments. The architecture comprises of embedded block RAMs (BRAMs) with multipliers adjacent to them as shown infig.…”
mentioning
confidence: 99%
“…However, the purpose of this paper is to model the target architecture in order to partition the algorithm and to improve memory utilization, rather than a system design exploration. A greedy algorithm is proposed in [22] for mapping array references resident in computation critical paths onto FPGA on-chip memory resources to provide parallel data accesses for instruction-level parallelism. The algorithm only produces a locally optimal solution.…”
Section: Introductionmentioning
confidence: 99%