Memory interference characterization between CPU cores and integrated GPUs in mixed-criticality platforms

Cavicchioli, Roberto; Capodieci, Nicola; Bertogna, Marko

doi:10.1109/etfa.2017.8247615

Cited by 51 publications

(49 citation statements)

References 13 publications

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“…Pan et al [26] designed an LLC management strategy for better performance. Cavicchioli et al [4] studied different SoCs and fused CPU-GPU devices to characterize memory contention. Hill et al [10] extended the Roofline model for mobile SoCs to address memory contention from the perspective of PU BW usage.…”

Section: Related Work 81 Memory Contention Studiesmentioning

confidence: 99%

“…Collocated kernel execution on an iSMHS will likely cause contention on the shared memory bus, and the resulting interference could negatively affect perceived bandwidth (BW) on collocated kernels. Several studies [4,7,15,37] focused on identifying the memory access patterns of collocated kernels in CPU+GPU iSMHS and suggested smart scheduling mechanisms to minimize contention effects, mostly via ad hoc approaches. However, these approaches do not provide a systematic solution for systems with different heterogeneity characteristics and an arbitrary number of PUs.…”

Section: Introductionmentioning

confidence: 99%

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Mephesto

Monil

Belviranlı

Lee

et al. 2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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Integrated shared memory heterogeneous architectures are pervasive because they satisfy the diverse needs of mobile, autonomous, and edge computing platforms. Although specialized processing units (PUs) that share a unified system memory improve performance and energy efficiency by reducing data movement, they also increase contention for this memory since the PUs interact with each other. Prior work has investigated performance degradation due to memory contention, but few have studied the relationship of power and energy to memory contention. Moreover, a comprehensive solution that models memory contention for kernel placement on contemporary heterogeneous systems on chip (SoCs) in response to energy and performance has been largely unaddressed. This paper presents MEPHESTO, a novel and holistic approach for managing this balance. The authors characterize applications and PUs in terms of two memory contention factors-time factors and power factors-to achieve the desired trade-off between energy and performance for collocated kernel execution on heterogeneous systems. The authors believe that this investigation is the first to combine all of these factors and present a simple knobbased approach that expresses the target trade-off. The approach is evaluated on a diverse integrated shared memory heterogeneous system with a CPU, GPU, and programmable vision accelerator. By using an empirical model for memory contention that provides up to 92% accuracy, the kernel collocation approach can provide a near-optimal ordering and placement based on the user-defined, energy-performance trade-off parameter. Moreover, the dynamic programming-based heuristics provide up to 30% better energy or 20% performance benefits when compared with the greedy approaches commonly employed by previous studies.

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Section: Related Work 81 Memory Contention Studiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mephesto

Monil

Belviranlı

Lee

et al. 2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

View full text Add to dashboard Cite

show abstract

“…When both these clients access memory, contention at the level of the memory controller and within DRAM banks can cause a significant performance degradation to the observed applications, as concurrent access to memory devices is most commonly arbitrated with no real-time compliant mechanisms. In [9] a complete evaluation of the extent of memory contention is presented: Cavicchioli et al show that a GPU application can experience performance degradation up to 100% in case of intensive memory use from a CPU application and, specularly, performance degradation of a CPU application with an interfering GPU memory bounded activity can cause latencies increase of almost 6x. Tests were conducted in multiple commercial SoCs that features an integrated GPU, such as NVIDIA development boards (TX1 and TK1) and an Intel i7 processor.…”

Section: A Wcet Estimationmentioning

confidence: 99%

A Perspective on Safety and Real-Time Issues for GPU Accelerated ADAS

Olmedo

Capodieci

Cavicchioli

2018

IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society

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The current trend in designing Advanced Driving Assistance System (ADAS) is to enhance their computing power by using modern multi/many core accelerators. For many critical applications such as pedestrian detection, line following, and path planning the Graphic Processing Unit (GPU) is the most popular choice for obtaining orders of magnitude increases in performance at modest power consumption. This is made possible by exploiting the general purpose nature of today's GPUs, as such devices are known to express unprecedented performance per watt on generic embarrassingly parallel workloads (as opposed of just graphical rendering, as GPUs where only designed to sustain in previous generations). In this work, we explore novel challenges that system engineers have to face in terms of realtime constraints and functional safety when the GPU is the chosen accelerator. More specifically, we investigate how much of the adopted safety standards currently applied for traditional platforms can be translated to a GPU accelerated platform used in critical scenarios.

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“…Changes in the GPU-RLM communication infrastructure means implementing signals at each scheduling event related to an application: new work has been submitted, previous work has been consumed by GPU engines and the event of server budget expiration (A, B and C respectively in gure 2). We are also investigating methodologies to mitigate memory interference between CPU and GPU in embedded SoCs [1,2,4,5].…”

Section: Future Work On Virtualizationmentioning

confidence: 99%

Work-in-Progress: NVIDIA GPU Scheduling Details in Virtualized Environments

Capodieci

Cavicchioli

Bertogna

2018

2018 International Conference on Embedded Software (EMSOFT)

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Modern automotive grade embedded platforms feature high performance Graphics Processing Units (GPUs) to support the massively parallel processing power needed for next-generation autonomous driving applications. Hence, a GPU scheduling approach with strong Real-Time guarantees is needed. While previous research e orts focused on reverse engineering the GPU ecosystem in order to understand and control GPU scheduling on NVIDIA platforms, we provide an in depth explanation of the NVIDIA standard approach to GPU application scheduling on a Drive PX platform. Then, we discuss how a privileged scheduling server can be used to enforce arbitrary scheduling policies in a virtualized environment.

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Memory interference characterization between CPU cores and integrated GPUs in mixed-criticality platforms

Abstract: The terms and conditions for the reuse of this version of the manuscript are specified in the publishing policy. For all terms of use and more information see the publisher's website.

Cited by 51 publications

References 13 publications

Mephesto

Mephesto

A Perspective on Safety and Real-Time Issues for GPU Accelerated ADAS

Work-in-Progress: NVIDIA GPU Scheduling Details in Virtualized Environments

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