Memory‐efficient SURF architecture for ASIC implementation

Abstract

Among the image features for object recognition, speeded up robust features (SURF) have been widely implemented due to their hardware-friendly characteristics and high accuracy. However, because of adopting a fully internal memory-based architecture and a field programmable gate array having large memories for a high performance, most of them are infeasible to the application specific integrated chip (ASIC). A memory-efficient architecture for implementing SURF in ASIC by analysing the characteristics of memory accesses of SURF is presented. In addition, a strategy of dividing an entire image into multiple sub-images, processing them sequentially and overlapping each other to reduce the size of the internal memory while minimising the loss of information is proposed. The proposed architecture was implemented with 767 kb-sized internal memories and 1.2 M logic gates while processing 60 frames per second.

Reconfigurable hardware architecture for faster descriptor extraction in SURF

“…To demonstrate the performance improvement by the proposed architecture, we have evaluated its performance with increasing the gap between the numbers of interest points on two images that are shown as the six cases of interest point ratio in Table 2. In all six of these cases, the base architecture as [2, 3] shows the same performance because its performance is always bounded by the descriptor extraction step processing more interest points. However, the proposed architecture improves performance by 24.77–47.45% when the interest point ratio increases because of the wider gap between the numbers of interest points, the further accelerated descriptor extraction step processing more interest points is by utilising the idle accelerator modules.…”

“…Among existing feature extraction algorithms, speeded up robust features (SURFs) [1] are considered to be the most efficient feature extraction algorithm because SURF has properties such as scale/rotation invariance and robustness to illumination changes. The SURF algorithm has been implemented in powerful hardware [2,3] for real-time operation on various computer vision systems due to its characteristics of data-intensive computation of high complexity. Especially, the computational load of the descriptor extraction step is very significant and the overall performance of SURF can be improved by speeding up this step with increasing parallel hardware accelerators.…”

Scale-Optimized Surface Roughness for Topographic Analysis

“…Therefore, multi-gigabyte DEMs may not be able to be processed on memory-constrained systems without first splitting the data into smaller pieces. Memory usage issues associated with the application of integral images have been widely recognized in the literature [27,28]. This may become less of a restrictive issue as computing platforms with greater memory become more commonly available and as researchers continue to move toward cloud computing platforms, such as Google Earth Engine, for spatial analysis [29].…”

Fast descriptor extraction method for a SURF‐based interest point

“…We can see that d(C, A) and d(B, D) are repeatedly computed in (5) and (6). This demonstrates that the computations of H h and H v based on (2) and (3) contain unnecessary operations.…”

“…Hence, a lot of research has been performed on applying the SURF algorithm to real-time applications. These studies have mainly focused on designing efficient hardware architecture [2,3] and developing parallel computing-based software solution [4,5].…”