Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications

Caselli, Michele; Debacker, Peter; Boni, Andrea

doi:10.1109/tcsii.2022.3174622

Cited by 4 publications

(7 citation statements)

References 33 publications

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“…3(b) the F-1T1R normalized current variation ∆I/I L vs I L . A large ∆I corresponds to a larger signal on the summation line, which relaxes the ADC specifications [2]. From the simulations, ∆I/I L is maximized in W.I.…”

Section: F-2t2r: a Novel Cell For Tia-less And Highly Parallel Rram-b...mentioning

confidence: 88%

“…The scheme in Fig. 2(a) includes a digital-to-time D/A converter (DAC) to drive the gates of the MOS switches of the 1T1R cells, on the same row, with the pulse-width modulated (PWM) signal V DD • act i (t) 1 [2]. The length of the pulse is proportional to the activation value, i.e., T M AC • a i with a i ∈ [0, 1].…”

Section: F-2t2r: a Novel Cell For Tia-less And Highly Parallel Rram-b...mentioning

confidence: 99%

“…In recent years, mixed-signal accelerators have emerged as a valuable solution to maximize throughput and energy efficiency, in DNN algorithm execution. These processing units operate with low precision operands, obtaining high classification accuracy, with a great reduction of energy consumption [2]. Accelerators exploit the concept of Analog in-Memory Computation (AiMC) to reduce data movement between memory and processor [3].…”

Section: Introductionmentioning

confidence: 99%

“…By the inclusion of these memories, mixed-signal accelerators can outperform the standard SRAM-based implementations, at the cost of additional challenges in process integration and circuit A. Boni, F. Malena, F. Saccani, M. Amoretti, and M. Caselli are with the Department of Engineering and Architecture, University of Parma, 43124 Parma, Italy (e-mail: andrea.boni@unipr.it). design [2]. Among non-standard devices, Resistive Random Access Memory (RRAM) are non-volatile, with potential high memory density, and can offer multi-bit weight capability [4].…”

Section: Introductionmentioning

confidence: 99%

“…The low value of the programmable resistance is particularly critical for the computation linearity, making the MVM result severely affected by the IR drop along the column. This forces countermeasures in hardware, including integrator circuit or transimpedance amplifier (TIA) to clamp SL, with penalties for accelerator area and energy consumption [2]. Reducing the number of cells in computation can also alleviate this issue, but it also reduces the energy efficiency [7].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications

Boni,

Malena,

Saccani

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This paper presents the Flipped (F)-2T2R RRAM compute cell enhancing the performance of RRAM-based mixedsignal accelerators for deep neural networks (DNNs) in machine learning (ML) applications. The F-2T2R cell is designed to exploit the features of the FD-SOI technology and it achieves a large increase in cell output impedance, compared to the standard 1T1R cell. The paper also describes the modelling of an F-2T2Rbased accelerator and its transistor-level implementation in a 22nm FD-SOI technology. The modelling results and the accelerator performance are validated by simulation. The proposed design can achieve an energy efficiency of up to 1260 1b-TOPS/W, with a memory array of 256 rows and columns. From the results of our analytical framework, a ResNet18, mapped on the accelerator, can obtain an accuracy reduction below 2%, with respect to the floating point baseline, on the CIFAR-10 dataset.

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Section: F-2t2r: a Novel Cell For Tia-less And Highly Parallel Rram-b...mentioning

confidence: 88%

Section: F-2t2r: a Novel Cell For Tia-less And Highly Parallel Rram-b...mentioning

confidence: 99%