Memory controller architectures: A comparative study

Khalifa, Khaled Ben; Fawzy, Haytham; El-Ashry, Sameh; Salah, Khaled

doi:10.1109/idt.2013.6727083

Cited by 9 publications

(3 citation statements)

References 2 publications

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“…The AMBA AHB RTL is modeled using Verilog (3 masters and 4 slaves). The design verification is then carried out by making use of assertions and the binding construct using ModelSim [9]. Binding enables addition of assertions to design without modifying the RTL design files.…”

Section: Literature Surveymentioning

confidence: 99%

A System Verilog Approach for Verification of Memory Controller

P¹

2020

IJERT

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The major bottleneck of the computer system to improve the overall performance, is the memory performance. An effective control of data between processor and memory can be done using memory controller. Verification plays a vital role in any design flow as it is completed before silicon development. In this work a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically ErasableProgrammable Read-Only Memory is designed and a Constraint random verification environment which is coverage driven, is built for the designed memory controller. The code is written in Verilog HDL and the verification is done using System Verilog. Using Questa Sim 10.0b software tool the simulation is done, and coverage results are obtained. The verification environment built in this work, gives a functional coverage of 96.8% and assertion success of 100% with 0% assertion failures. Simulation results show that the designed controller gave good performance and full filled all the system specifications.

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Section: Literature Surveymentioning

confidence: 99%

A System Verilog Approach for Verification of Memory Controller

P¹

2020

IJERT

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“…The HMC also supports PIM in order to mitigate data movement between memory and processor, where processing occurs in the same chip from the memory. Thus, many researchers are evaluating performance and energy consumption of existing HMC [Jeddeloh and Keeth 2012], [Khalifa et al 2013], [Hadidi et al 2017] or proposed new PIM architectures [Pugsley et al 2014], [Alves et al 2016].…”

Section: Introductionmentioning

confidence: 99%

Intrinsics-HMC: An Automatic Trace Generator for Simulations of Processing-In-Memory Instructions

Cordeiro¹,

Kepe²,

Tomé³

et al. 2017

Anais Do XVIII Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2017)

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Processor-in-Memory (PIM) architectures, such as the Hybrid Memory Cube (HMC), are emerging nowadays as a solution for processing large amount of data directly inside the memory. In this area, several researchers are proposing and evaluating new instructions and new PIM architectures. For such evaluations, trace-driven simulators, as the Simulator of Non-Uniform Cache Architectures (SiNUCA), are commonly used in order to model these new proposed systems. Such simulators provide fast prototyping of new architectures, while it requires the researcher to write simulation traces manually when evaluating new Instruction Set Architecture (ISA) proposals, which is an time consuming and error prone task. In this work, we propose a methodology for fast generation of simulation traces focused on HMC architecture, which consists on a high-level Intrinsics-HMC library and a modification inside the trace-generator tool from SiNUCA. Our proposal enables the researchers to write high level code in C/C++ languages using our library, which mimics the behavior of HMC instructions. These codes can be compiled and executed in traditional x86 architectures for verification. After ensure the code is correct and working, the user can use our modified version of SiNUCA-Tracer to translate HMC functions into HMC instructions know by the simulator, providing a convenient solution to generate traces and fast simulations of new PIM architectures. Results using the proposed technique applied on database application kernels show the correct translation and simulation of new HMC instructions using SiNUCA.

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“…This universal memory controller proposes six different partitions which are boot, enhanced, system code, high speed, temporary and the user data area partition to benefit from the permanent storage of the controlled memory as; for example; the log feature exploits the high speed partition to reduce the access consumed power and minimize the access time of the most frequently used data, and the hibernate power level in Fig.2 exploits the temporary partition to store the last status of the universal memory controller before it is turned off [9]- [10]. Fig.3 The expected d data from the mory controller.…”

Section: Introductionmentioning

confidence: 99%

Implementation and verification of a generic universal memory controller based on UVM

Khalifa

Salah²

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Abstract‫ـــــ‬ This paper presents a coverage driven constraint random based functional verification method based on the Universal Verification Methodology (UVM) using System Verilog for generic universal memory controller architecture. This universal memory controller is looking forward to improving the performance of the existing memory controllers through a complete integration of the existing memory controllers features in addition of providing novel features. It also reduces the consumed power through providing high power consumption control due to its proposed different power levels supported to fit all power scenarios. While implementing a worthy architecture like the proposed generic universal memory controller, UVM is the best choice to build well-constructed, high controlled and reusable verification environment to efficiently verify it. More than 200 coverage points have been covered to verify the validation of the integrated features which makes the proposed universal memory controller replaces the existing controllers on the scene as it provides all of their powerful features in addition of novel features to control two of the most dominated types of memory; FLASH and DRAM through one memory controller.

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Memory controller architectures: A comparative study

Cited by 9 publications

References 2 publications

A System Verilog Approach for Verification of Memory Controller

A System Verilog Approach for Verification of Memory Controller

Intrinsics-HMC: An Automatic Trace Generator for Simulations of Processing-In-Memory Instructions

Implementation and verification of a generic universal memory controller based on UVM

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