Memory-Aware Scheduling for Mixed-Criticality Systems

Zheng, Lirong; Wang, Li

doi:10.1007/978-3-319-42108-7_11

Cited by 4 publications

(3 citation statements)

References 17 publications

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“…As an example, task parameters required for modelling MCS with the resource usage scenario for both unicore and multi-core systems can be categorized into three main functional attributes namely, shared resource usage, resource synchronization and communication (message passing). When considering shared resources such as memory, the basic task model (Vestal, 2007) is extended with parameters like minimum/maximum number of memory accesses (Pellizzoni et al, 2010), worst case number of cache misses (Yun et al, 2012), worst case memory access time (Li & Wang, 2016), worst case number of L1/LL cache misses (Nair et al, 2019), number of memory accesses (Awan et al, 2018) and intra/inter-core blocking times (Burns, 2013;Nair et al, 2019). Resource synchronization includes parameters like blocking times (Burns, 2013) (Burns & Davis, 2013) and worst case communication time (WCCT) (Dridi et al, 2019).…”

Section: Setup Phasementioning

confidence: 99%

Sacred

Colaco

Nair

Madnawat

et al. 2023

International Journal of E-Collaboration

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Collaborative research is an opportunity to bring creative minds together and blend multiple disciplines to churn out innovative solutions. In this era of massive social media and information overload, a streamlined process framework with best practices and procedures is a requirement for genuine scientific collaboration. The main aim of this work is to bring forth a software-centric framework for harmonizing research. SACRED is the outcome of experiences gained during the development of ‘ARMS'-An Analysis Framework for Mixed Criticality Systems. ARMS is a collaborative platform to disseminate research and literature in real-time mixed criticality systems. ARMS is hosted on Amazon Amplify with the user interface implemented using the ReactJS framework. SACRED summarizes the software-centric process, practices and procedures followed, and renders it for similar collaborations in the future.

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Section: Setup Phasementioning

confidence: 99%

Sacred

Colaco

Nair

Madnawat

et al. 2023

International Journal of E-Collaboration

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“…If the volume of requests and data is criticality dependent then analysis similar to that used for processor scheduling can be applied. The separation of execution time from memory-access time is explored by Li and Wang [2016]. They demonstrate that this distinction improves schedulability.…”

Section: Communication and Other Resourcesmentioning

confidence: 99%

A Survey of Research into Mixed Criticality Systems

2017

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This survey covers research into mixed criticality systems that has been published since Vestal's seminal paper in 2007, up until the end of 2016. The survey is organised along the lines of the major research areas within this topic. These include single processor analysis (including fixed priority and EDF scheduling, shared resources and static and synchronous scheduling), multiprocessor analysis, realistic models, and systems issues. The survey also explores the relationship between research into mixed criticality systems and other topics such as hard and soft time constraints, fault tolerant scheduling, hierarchical scheduling, cyber physical systems, probabilistic real-time systems, and industrial safety standards. CCS Concepts: •Computer systems organization → Real-time system specification; •Software and its engineering → Real-time schedulability; Real-time systems software;

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“…To that end, we employ and combine known machine learning (ML) techniques: in this work we exploit Support Vector machines for Regression (SVR) [5], Random Forest Regressor (RFR) [6] and Deep Neural Network (DeepNN) [7]. Being able to understand, in a data driven fashion, the important factors that are involved in memory interference and thus predict kernel latency degradation are paramount to derive an accurate response time analysis [8], [9]. This paper is structured as follows: In Section II, we present the related work.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Techniques for Understanding and Predicting Memory Interference in CPU-GPU Embedded Systems

Masola,

Capodieci,

Rouxel

et al. 2023

2023 IEEE 29th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

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Nowadays, heterogeneous embedded platforms are extensively used in various low-latency applications, including the automotive industry, real-time IoT systems, and automated factories. These platforms utilize specific components, such as CPUs, GPUs, and neural network accelerators for efficient task processing and to solve specific problems with a lower power consumption compared to more traditional systems. However, since these accelerators share resources such as the global memory, it is crucial to understand how workloads behave under high computational loads to determine how parallel computational engines on modern platforms can interfere and adversely affect the system's predictability and performance. One area that remains unclear is the interference effect on shared memory resources between the CPU and GPU: more specifically, the latency degradation experienced by GPU kernels when memory-intensive CPU applications run concurrently. In this work, we first analyze the metrics that characterize the behavior of different kernels under various board conditions caused by CPU memory-intensive workloads on a Nvidia Jetson Xavier. Then, we exploit various machine learning methodologies aiming to estimate the latency degradation of kernels based on their metrics. As a result of this, we are able to identify the metrics that could potentially have the most significant impact when predicting the kernels completion latency degradation.

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Memory-Aware Scheduling for Mixed-Criticality Systems

Cited by 4 publications

References 17 publications

Sacred

Sacred

A Survey of Research into Mixed Criticality Systems

Machine Learning Techniques for Understanding and Predicting Memory Interference in CPU-GPU Embedded Systems

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