Memory Analysis of Low Power MPEG-4 Decoder Architecture

Dahlin, Andreas; Ersfolk, Johan; Habli, Haitham; Lilius, Johan

doi:10.1109/icess.2009.85

Cited by 5 publications

(5 citation statements)

References 8 publications

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“…The amount of memory transfers between local memories amount to I gigabyte. In [13], the improved architecture for the MPEG-4 decoder was proved to be better from the point of memory transfers. The total amount of data transfers decreased by 40% from 2.2 gigabytes to l.3 gigabytes.…”

Section: Introductionmentioning

confidence: 98%

“…The additional memory reads for inter-coded frames originates from the motion compensation operation, in which one or two reference frames must be accessed in order to produce a motion compensated macroblock. The complete memory analysis, including detailed input/output information for macroblocks originating from P-VOPs and B-VOPs can be found in [13]. The accelerators can only access data stored in the local memories (SRAM), hence a data transfer must be initiated by the general purpose processor in order to transfer data between main memory (DRAM) and the local memories.…”

Section: Introductionmentioning

confidence: 99%

“…In [13], a improved architecture of the hardware accel erated MPEG-4 decoder was introduced, see Figure 1. The improvement was with respect to the memory scheme and data transfer between accelerators.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analysis of memory access optimization for motion compensation frames in MPEG-4

Habli

Lilius

Ersfolk

2009

2009 International Symposium on System-on-Chip

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Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

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Analysis of memory access optimization for motion compensation frames in MPEG-4

Habli

Lilius

Ersfolk

2009

2009 International Symposium on System-on-Chip

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“…The motion compensation module is the most intensive part of accessing memory and has the highest throughput. And memory optimization is of great importance for performance and power/cost [4,5]. As to this problem, a special pixel buffer was proposed to avoid repeating accessing memory and a corresponding fraction pixel interpolation unit with parallel structure was designed, so that the whole motion compensation module can work in efficient performance.…”

Section: Introductionmentioning

confidence: 99%

An efficient VLSI architecture and implementation of motion compensation for MPEG-4

Zhang

Song

et al. 2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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An efficient VLSI architecture of motion compensation of MPEG-4 is presented in this paper. Aiming at the memory accessing problem of the motion compensation, three special methods were adopted. First, a novel interpolation pixel buffering mechanism and the corresponding parallel interpolation structure were proposed to save the buffering storage consumption of the interpolation pixels distinctly. Second, a modified method of motion vector decoding was adopted, which uses row buffer instead of storing the entire motion vectors of the whole frame, and can saves about 85% of the motion vector storage space. Third, method of hardware based unrestricted motion compensation was also discussed, using coordinate transformation to avoid pixel reproduction, can save both memory usage and memory accessing times. The design has been described by Verilog HDL and was implemented based on Field Programmable Gate Array (FPGA). Integrated with the motion compensation module, the whole MPEG-4 decoder can operate correctly.

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“…The motion estimation module is the most intensive part of accessing memory and has the highest throughput. Memory optimization is of great importance for performance and power/cost [5,6]. To this problem, some memory optimization efforts have been tried in this paper, including a 3-stage pipeline structure which can improve the parallel ability of motion estimation process and make full use of memory access bandwidth, a modified memory organization strategy for off chip SDRAM access efficiency, and a shared cyclic search window memory which can reduce on chip memory resource and cycles of memory access.…”

Section: Introductionmentioning

confidence: 99%

Design and Memory Optimization of Motion Estimation Module for H.264/AVC Encoder

Zhang

Wang

Song

et al. 2011

AMR

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H.264/AVC standard has been widely used in video compression at various kinds of application domain. Motion estimation takes the most calculation workload of H.264/AVC encoder. Memory optimization has played an even more important role in encoder design. Firstly, dependency relation between motion vectors was analyzed and removed at a little cost of estimation accuracy decrement, and then a 3-stage macro-block level pipeline architecture was proposed to increase parallel process ability of motion estimation. Then an optimized memory organization strategy of reference frame data was put forward, aiming at avoiding row changing frequently in SDRAM access. Finally, based on the 3-stage pipeline structure, a shared cyclic search window memory was proposed: 1) data relativity between adjacent macro-block was analyzed, 2) and search window memory size was elaborated, 3) and then a slice based structure and the work process were discussed. Analysis and experiment result show that 50% of on chip memory resource and cycles for off chip SDRAM access can be saved. The whole design was implemented with Verilog HDL and integrated into a H.264 encoder, which can demo 1280*720@30 video successfully at frequency of 120MHz under a cyclone III FPGA development board.

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Memory Analysis of Low Power MPEG-4 Decoder Architecture

Cited by 5 publications

References 8 publications

Analysis of memory access optimization for motion compensation frames in MPEG-4

Analysis of memory access optimization for motion compensation frames in MPEG-4

An efficient VLSI architecture and implementation of motion compensation for MPEG-4

Design and Memory Optimization of Motion Estimation Module for H.264/AVC Encoder

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