Memory Access Patterns for the Analysis of MPSoCs

Schliecker, Simon; Ivers, Matthias; Ernst, Rolf

doi:10.1109/newcas.2006.250943

“…The aim of the above discussion and this entire chapter is to establish some characteristics and formal requirements for on-chip communications. As the previous section shows, most on-chip protocols are transaction-based and go through specific stages, which makes it possible to establish a relationship between the latency of a transaction (the time taken for a transaction to complete) and the achievable throughput of an interface such as [15,16].…”

Section: On-chip Communication Characteristicsmentioning

confidence: 99%

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Dumitriu¹

2021

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0

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The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

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“…The aim of the above discussion and this entire chapter is to establish some characteristics and formal requirements for on-chip communications. As the previous section shows, most on-chip protocols are transaction-based and go through specific stages, which makes it possible to establish a relationship between the latency of a transaction (the time taken for a transaction to complete) and the achievable throughput of an interface such as [15,16].…”

Section: On-chip Communication Characteristicsmentioning

confidence: 99%

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Dumitriu¹

2021

Preprint

0

View full text Add to dashboard Cite

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

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“…The main idea is to separate the timing analysis procedure into three disjoint steps: ( 1 ) First, the load imposed by tasks on shared resourcesη has to be determined. By considering the pattern of task activations η and the distance between requests issued by each task, the overall load imposed on the shared resource can be derived for each task and all tasks on a processor 1), 60) . Depending on the accuracy of the request model, the analysis of the shared resource delay can vary significantly, because if larger request distances can be formally guaranteed, many conflicts can potentially be ruled out.…”

Section: Mpsoc Analysis In Presence Of Shared Resourcesmentioning

confidence: 99%

Mastering MPSoCs for Mixed-critical Applications

Axer

¹

,

Diemer

²

,

Negrean

³

et al. 2011

IPSJ Transactions on System LSI Design Methodology

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Multi-Processor Systems-on-Chips (MPSoCs) emerge as the predominant platform in embedded real-time applications. A large variety of ubiquitous services should be implemented by embedded systems in a cost-and powerefficient way, yet providing a maximum degree of performance, usability and dependability. By using a scalable Network-on-Chip (NoC) architecture which replaces the traditional point-to-point and bus connections in conjunction with performant IP cores it is possible to use the available performance to consolidate functionality on a single MPSoC platform. But especially when uncritical best-effort applications (e.g., entertainment) and critical applications (e.g., pedestrian detection, electronic stability control) are combined on the same architecture (mixed-criticality), validation faces new challenges. Due to complex resource sharing in MPSoCs the timing behavior becomes more complex and requires new analysis methods. Additionally, applications that may exhibit multiple behaviors corresponding to different operating modes (e.g., initialization mode, fault-recovery mode) need to be also considered in the design of mixed-critical MPSoCs. In this paper, challenges in the design of mixed-critical systems are discussed and formal analysis solutions which consider shared resources, NoC communication, multi-mode applications and their reliabilities are proposed.

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Memory Access Patterns for the Analysis of MPSoCs

Cited by 11 publications

References 5 publications

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

Mastering MPSoCs for Mixed-critical Applications

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