2018
DOI: 10.1007/978-3-319-76953-0_2
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MemJam: A False Dependency Attack Against Constant-Time Crypto Implementations in SGX

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Cited by 33 publications
(42 citation statements)
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“…While there is a long line of work on dismantling SGX's confidentiality guarantees [69,11,46,73,50,25,72] as well as exploiting classical memory safety vulnerabilities in enclaves [45,8,70], Plundervolt represents the first attack that directly violates SGX's integrity guarantees for functionally correct enclave software. By directly breaking ISAlevel processor semantics, Plundervolt ultimately undermines even relaxed "transparent enclaved execution" paradigms [66] that solely require integrity of enclave computations while assuming unbounded side-channel leakage.…”
Section: Discussion and Related Workmentioning
confidence: 99%
See 1 more Smart Citation
“…While there is a long line of work on dismantling SGX's confidentiality guarantees [69,11,46,73,50,25,72] as well as exploiting classical memory safety vulnerabilities in enclaves [45,8,70], Plundervolt represents the first attack that directly violates SGX's integrity guarantees for functionally correct enclave software. By directly breaking ISAlevel processor semantics, Plundervolt ultimately undermines even relaxed "transparent enclaved execution" paradigms [66] that solely require integrity of enclave computations while assuming unbounded side-channel leakage.…”
Section: Discussion and Related Workmentioning
confidence: 99%
“…To limit the performance penalty of such an approach, we propose leveraging commodity Hy-perThreading [36] features in Intel CPUs and turn them from a security concern into a security feature for fault resistancy. After a long list of SGX attacks [69,75,59,50] demonstrated how enclave secrets can be reconstructed from a sibling CPU core, Intel officially recommended disabling hyperthreading when using SGX enclaves [32]. However, this also imposes a significant performance impact on any non-SGX workloads.…”
Section: Countermeasuresmentioning
confidence: 99%
“…Prior work has shown that the L1 dTLB can be exploited for a reliable side-channel attack through the TLB [7] using a PRIME+PROBE-style attack. Memory Order Buffer (MOB) is yet another shared resource that can leak information by creating a false dependency across threads [43] and stalling the victim thread while the CPU decides whether store forwarding should proceed (in case of a true dependency).…”
Section: Related Workmentioning
confidence: 99%
“…An example was an aliasing issue caused by a stack store instruction at the beginning of the Spectre gadget. When the given load address to leak from happened to 4k-alias the address of the earlier stack store instruction, a stall introduced by the store-to-load forwarding logic [67,83] disrupted the signal. To address this issue, an option is to chain together multiple speculative gadgets [8] and perform stack pivoting before executing the Spectre gadget.…”
Section: Exploit 3: Breaking Software-based Xommentioning
confidence: 99%
“…Microarchitectural attacks. While early microarchitectural attacks such as classic cache side-channel attacks [69,98] or even more recent attacks [5,24,37,38,67,93] primarily focus on breaking crypto implementations, there is a large body of work on microarchitectural attacks to support software exploitation. Such attacks typically use side-channel disclosure to mimic limited memory read primitives [12,26,39] and fault attacks like Rowhammer to mimic limited memory write primitives [12,20,28,29,42,72,76,85,86,92].…”
Section: Related Workmentioning
confidence: 99%