Member Tampering Attack on Burmester-Desmedt Group Key Exchange Protocol and Its Countermeasure

Sun, Da‐Zhi; Tian, Yangguang

doi:10.3390/math10193685

Cited by 1 publication

(1 citation statement)

References 30 publications

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“…This fabricated example shows the overly lengthy inverter delay's part in producing an output glitch, yet a glitch would still arise regardless of the delay time. It is evident from the timing diagram how the inverter delay is connected to the output glitch (Sun & Tian, 2022).…”

Section: Logic Glitchesmentioning

confidence: 99%

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

Ehis¹

2023

Braz. J. of Sci.

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The last century has seen an evolution in technology that has improved communication systems and, in general, made life easier for people. Our communication systems have become faster and more dependable as a result of the explosion of gadgets and services. But, these upgrades come at a price. The power consumption is one of the most worrying costs. In recent years, the solution involved installing larger, more powerful batteries—so long as doing so did not limit mobility. Today's economic and environmental problems compel us to consider alternative solutions, like methods for lowering the power consumption of digital devices. This study focuses on using digital circuits, which promise to deliver good energy efficiency and desirable performance at very low voltage savings. Certain digital switches are allegedly redundant and not required for the circuit to function properly, yet they continue to use energy. So, one of the primary issues for low power design is reducing such redundant switches. Subthreshold conduction in digital circuits is typically seen as a “parasitic” leakage in a condition where there should ideally be no conduction. Sub-threshold activities thereby reduce the problem of lowering power consumption, but do so at the expense of system throughput deterioration, fluctuations in system stability and functionality, temperature variations, and most critically, design space utilization. In order to minimize some of these redundant switches and to make circuits more energy-efficient while maintaining functionality, this study suggests two novel techniques. It uses an optimization method based on threshold voltage change to reduce glitch power. A glitch-free circuit netlist is created using an algorithm, while still maintaining the requisite delay performance. Using this approach results in a 6.14% overall reduction in energy consumption.

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Section: Logic Glitchesmentioning

confidence: 99%

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

Ehis¹

2023

Braz. J. of Sci.

View full text Add to dashboard Cite

show abstract

Member Tampering Attack on Burmester-Desmedt Group Key Exchange Protocol and Its Countermeasure

Cited by 1 publication

References 30 publications

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

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