MeLPUF: Memory in Logic PUF

Abstract

Physical Unclonable Functions (PUFs) are used for securing electronic designs across the implementation spectrum ranging from lightweight FPGA to server-class ASIC designs. However, current PUF implementations are vulnerable to model-building attacks; they often incur significant design overheads and are challenging to configure based on application-specific requirements. These factors limit their application, primarily in the case of the system on chip (SoC) designs used in diverse applications. In this work, we propose MeL-PUF -Memory-in-Logic PUF, a low-overhead, distributed, and synthesizable PUF that takes advantage of existing logic gates in a design and transforms them to create cross-coupled inverters (i.e. memory cells) controlled by a PUF control signal. The power-up states of these memory cells are used as the source of entropy in the proposed PUF architecture. These on-demand memory cells can be distributed across the combinational logic of various intellectual property (IP) blocks in a system on chip (SoC) design. They can also be synthesized with a standard logic synthesis tool to meet the area/power/performance constraints of a design. By aggregating the power-up states from multiple such memory cells, we can create a PUF signature or digital fingerprint of varying size. We evaluate the MeL-PUF signature quality with both circuit-level simulations as well as with measurements in FPGA devices. We show that MeL-PUF provides high-quality signatures in terms of uniqueness, randomness, and robustness, without incurring large overheads. We also suggest additional optimizations that can be leveraged to improve the performance of MeL-PUF .

FLEX PUF: A Flexible Physical Unclonable Function Design Using Configurable Templates

“…By shifting their values and measuring the delay between them, this PUF design provides a reliable and unpredictable signature. Similarly, an FPGAbased memory PUF was proposed in [21] that models the behavior of an SRAM cell using reconfigurable LUTs to form a bistable loop. During power-up, the PUF elements enter a metastable state, settling on a consistent yet unpredictable value.…”

“…For this, we propose a PUF structure that offers a hybrid between a strong and weak PUF. This involves utilizing a single-response PUF mapped to the FPGA, which offers the same protection against machine learning attacks as an SRAM PUF [21]. However, as the PUF elements can be reconfigured, the elements used to generate the PUF response can be changed, which, in turn, changes the PUF response.…”