Mechanisms of charged-device electrostatic discharges

Renninger, R.G.

doi:10.1016/0304-3886(92)90076-6

Cited by 46 publications

(5 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The charged device model (CDM) pulse is regarded as the fastest event of all the ESD events [4,[12][13][14][15]. Note that the CDM pulse waveform is influenced by the test platform and measurement metrology.…”

Section: Charged Device Model (Cdm)mentioning

confidence: 99%

See 1 more Smart Citation

Electrostatic Discharge, Electrical Overstress, and Latchup in VLSI Microelectronics

Voldman¹

2020

Emerging Micro - And Nanotechnologies

View full text Add to dashboard Cite

Electrostatic discharge (ESD), electrical overstress (EOS), and latchup have been an issue in devices, circuit and systems for VLSI microelectronics for many decades and continue to be an issue till today. In this chapter, the issue of ESD, EOS and latchup will be discussed. This chapter will address some of the fundamental reasons decisions that are made for choice of circuits and layout. Many publications do not explain why certain choices are made, and we will address these in this chapter. Physical models, failure mechanisms and design solutions will be highlighted. The chapter will close with discussion on how to provide both EOS and ESD robust devices, circuits, and systems, design practices and procedures. EOS sources also occur from design characteristics of devices, circuits, and systems.

show abstract

Section: Charged Device Model (Cdm)mentioning

confidence: 99%

“…Electrical overstress (EOS) sources exist from natural phenomena and power distribution [1,[14][15][16][17][18][19][20][21][22][23][24][25]. Switches, cables, and other power electronics can be a source of electrical overstress.…”

Section: Qualification Of Semiconductor Components-electrical Overstrmentioning

confidence: 99%

Electrostatic Discharge, Electrical Overstress, and Latchup in VLSI Microelectronics

Voldman¹

2020

Emerging Micro - And Nanotechnologies

View full text Add to dashboard Cite

show abstract

“…The new joint standard will preserve test systems in the field, and improve the waveform measurement process. The charged device model (CDM) pulse is regarded as the fastest event of all the ESD events [4,[12][13][14][15]. Note that the CDM pulse waveform is influenced by the test platform and measurement metrology.…”

Section: Charged Device Model (Cdm)mentioning

confidence: 99%

“…Electrical overstress (EOS) sources exist from natural phenomena, and power distribution [1,[14][15][16][17][18][19][20][21][22][23][24][25]. Switches, cables, and other power electronics that can be a source of electrical overstress.…”

Section: Electrical Overstress (Eos)mentioning

confidence: 99%

System and Component Failure from Electrical Overstress and Electrostatic Discharge

Voldman¹

2018

System of System Failures

View full text Add to dashboard Cite

Electrical overstress (EOS) and electrostatic discharge (ESD) have been an issue in devices, circuit and systems for electronics for many decades, as early as the 1970s, and continued to be an issue to today. In this chapter, the issue of EOS and ESD will be discussed. The sources of both EOS and ESD failure history will be discussed. EOS and ESD physical models, failure mechanisms, testing methods and solutions will be shown. The chapter will close with discussion on how to provide both EOS and ESD robust devices, circuits, and systems, design practices, and procedures, as well as EOS and ESD factory control programs. EOS sources also occur from design characteristics of devices, circuits, and systems.

show abstract

“…Over 20 years passed after an appearance of CDM testing which is one of ESD testing method for semiconductor device. Various types of CDM testers were developed and phased-in as CPM (Charged package model), Field-induced CDM tester and mercury (Hg) relay type direct charged CDM tester [1][2][3][4][5][6][7][8][9][10][11]; we are investigating the fundamental consideration of the parameters for CDM destruction since CDM tester developed [12]. Some reports about re-consideration about for CDM tester specification and testing method tend to be appeared recently [13].…”

Section: Introductionmentioning

confidence: 99%

Consideration for CDM breakdown and reliability designing in the latest semiconductor technology

Wakai

Kobira

2009

2009 Annual Reliability and Maintainability Symposium

View full text Add to dashboard Cite

& CONCLUSIONSCDM (Charged Device Model) is still concerned reliability topic of ESD (Electrostatic Discharge). ESD breakdown voltage tends to lower with Silicon technology down scaling because of lack of energy change in source of ESD stress. Severity for the recent device and reality for actual situation are the reasons why many engineers are investigating aggressively. Fundamental consideration for CDM (Charged Device Model) in the point of breakdown and reliability designing were investigated with the recent semiconductor technology to achieve good endurant device for CDM.According to the result of failure analysis for CDM failed semiconductor device, it was found that gate oxide breakdown was critical failure mode in CDM. For the parameters investigation, Peak intensity and rise time of discharge current are well correlated their package capacitance. To consider this discharge phenomenon in the points of protection circuit, device and package is effective method to achieve well reliable design for CDM breakdown.Moreover there is further investigation. Increasing zapping time in CDM test causes breakdown voltage lowering, which mechanism is similar to that of TDDB for gate oxide breakdown. There is a tendency that an enlargement of semiconductor product scale which is represented with increasing of IC-pin number raises total zapping times in CDM test. Then, excessive CDM zapping stress accumulates its damage into critical gate oxide film and causes breakdown by lower voltage. This phenomenon might be near future concern.These result and consideration from our experiences are explained in this report.

show abstract

Mechanisms of charged-device electrostatic discharges

Cited by 46 publications

References 10 publications

Electrostatic Discharge, Electrical Overstress, and Latchup in VLSI Microelectronics

Electrostatic Discharge, Electrical Overstress, and Latchup in VLSI Microelectronics

System and Component Failure from Electrical Overstress and Electrostatic Discharge

Consideration for CDM breakdown and reliability designing in the latest semiconductor technology

Contact Info

Product

Resources

About