Mechanism Analysis of Ultralow Leakage and Abnormal Instability in InGaZnO Thin-Film Transistor Toward DRAM

Yan, Gangping; Yang, Hong; Liu, Weibing; Zhou, Na; Hu, Yanpeng; Shi, Yunchun; Gao, Jianfeng; Tian, Guoliang; Zhang, Yadong; Fan, Linjie; Wang, Guilei; Xu, Gaobo; Bi, Jinshun; Zhao, Chunjiang; Luo, Jun

doi:10.1109/ted.2022.3159266

Cited by 11 publications

(7 citation statements)

References 30 publications

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“…The extraction of VTH adopts the constant-current method in this work. The VTH is defined as the particular gate voltage (VG) at which drain current (ID) = 10 −8 × (W/L) A [24]. The µFE and SS of IGZO TFT is calculated according to the Equations The key electrical parameters that affect the static characteristics of IGZO TFT include threshold voltage (V TH ), field effect mobility (µ FE ), subthreshold swing (SS), and current switching ratio (I ON /I OFF ).…”

Section: Resultsmentioning

confidence: 99%

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

Wang,

Bi,

et al. 2024

Electronics

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The effect of high- and low-temperature conditions on the performance of IGZO TFT and logic circuits were investigated in this work. In the temperature range of 250−350 K, the performance of the IGZO TFT did not show significant changes and exhibited a certain degree of high- and low-temperature resistance. When the temperature was below 250 K, as the temperature decreased, the threshold voltage (VTH) of the IGZO TFT significantly increased, the field effect mobility (μFE) and the on state current (ION) significantly decreased. This is attributed to the lower excitation degree of charge carriers at extremely low temperatures, resulting in fewer charge carriers transitioning to the conduction or valence bands, and the formation of defects also limits carrier migration. When the temperature exceeded 350 K, as the temperature increased, more electrons could escape from the bandgap trap state and become free charge carriers, and the IGZO layer was thermally excited to produce more oxygen vacancies, resulting in higher μFE and lower VTH. In addition, the drain current noise spectral density of IGZO TFT conformed to the 1/ƒ noise characteristic, and the degradation mechanism of IGZO TFT over a wide temperature range was confirmed based on the changes in noise spectral density at different temperatures. In addition, an inverter logic unit circuit was designed based on IGZO TFT, and the performance changes over a wide temperature range were analyzed. This lays the foundation for IGZO TFT to be applied in integrated circuits with harsh environments.

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Section: Resultsmentioning

confidence: 99%

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

Wang,

Bi,

et al. 2024

Electronics

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“…[6] 큰 에너지 밴드 갭으로부터 기인된 low offcurrent 특성을 활용해 저전력 LTPO 디스플레이에 적 용하고 있음은 물론, 최근에는 저전력 DRAM용 트랜지 스터 채널막에도 도입을 검토하고 있는 단계이다. [7][8][9] 이처럼 짧은 시간 내에 눈부신 발전을 이루어 실제 산 업에 실제 응용되고 있는 n-type 산화물 반도체에 비해 다. [10] 이러한 내재적 문제가 극복될 수 있는 p-type 산 화물의 탐색과 실제 구현을 위한 연구가 수행되고 있 다.…”

Section: 서론unclassified

Recent progress of the p-type oxide thin films for transistor applications: Nickel oxide, Tin oxide, and Copper oxide

Choe¹,

Jeon²,

Hwang³

et al. 2023

Ceramist

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Over the past decade, many research groups have been striving to develop high-performance p-type switching oxide materials for implementing complementary metal–oxide–semiconductor (CMOS) thin film devices. However, realizing p-type oxide thin film transistors (TFTs) whose electrical properties are comparable to n-type oxide TFTs has been challenging. This is because of inherent characteristics of p-type oxide materials such as the high formation energy of native acceptors and high hole effective mass caused by localized hole transport path. Developing a p-type oxide with a delocalized hole transport pathway and low hole formation energy is crucial for the production of CMOS circuits utilizing oxide thin films. NiO, SnO, and CuO<sub>x</sub> are being actively studied as candidate materials that satisfy these requirements. This review discusses the latest advances in the synthesis method of p-type binary oxide thin films and the approach for electrical performance enhancement.

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“…Amorphous oxide semiconductors (AOSs) with extremely low off-currents originating from their electronic structure − have attracted considerable interest for applications in the storage chip industry, enabling the development of capacitorless dynamic random-access memory (DRAM) architecture and high-density DRAM technologies. − In contrast to thin-film transistors (TFTs) for flat panel displays, storage chips employ vertically stacked complex device architectures to achieve higher device density, − posing challenges in electrode processing, and increasing the importance of contact issues between AOSs and electrodes. − Process-derived poor contacts and a substantial Schottky barrier resulting from the intrinsic energy level mismatch between the work function of the electrode metal and the electron affinity of AOSs eventually lead to excessively high contact resistance ( R C ), thereby degrading field-effect mobility and power consumption. Recently, many works have proposed methods to solve high contact resistance between AOSs and metal electrodes, which may be categorized into several main strategies: additional deposition of a highly conductive oxide interlayer, − oxidation of the metal contact surface resulting in the formation of high concentration oxygen vacancies on the AOS contact surface via high-temperature annealing, − penetration of metal ions into the AOS layer, , and surface treatment with plasma. − These methods, which involve high-energy or multistep processes, offer effective solutions for the high contact resistance of the exposed upper surface of oxide semiconductors, as shown in Figure a, but are almost impossible to apply to buried contact or deep vertical interfaces within nanoscale complex structures.…”

Section: Introductionmentioning

confidence: 99%

Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway

Shi,

Tsuji,

Cho

et al. 2024

ACS Nano

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Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures offer promising alternative materials for next-generation high-density memory devices. The complex vertical stacking process of memory devices significantly increases the probability of encountering internal contact issues. Conventional surface treatment methods developed for planar devices necessitate efficient approaches to eliminate contact issues at deep internal interfaces in the nanoscale complex structures of AOS devices. In this work, we report the pioneering use of palladium thin film as a high-efficiency active hydrogen transfer pathway from the outside to the internal contact interface via low-temperature postannealing in the H 2 atmosphere, and the formation of highly conductive metallic interlayer effectively solves the contact issues at the deeply buried interfaces in devices. The application of this method reduced the contact resistance of Pd electrodes/amorphous indium−gallium−zinc oxide (a-IGZO) thin-film by 2 orders of magnitude, and thereby the mobility of thin-film transistor was increased from 3.2 cm 2 V −1 s −1 to nearly 20 cm 2 V −1 s −1 , preserving an excellent bias stress stability. This technology has wide applicability for the solution of contact resistance issues in oxide semiconductor devices with complex architectures.

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Mechanism Analysis of Ultralow Leakage and Abnormal Instability in InGaZnO Thin-Film Transistor Toward DRAM

Cited by 11 publications

References 30 publications

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

Characteristics Analysis of IGZO TFT and Logic Unit in the Temperature Range of 8–475 K

Recent progress of the p-type oxide thin films for transistor applications: Nickel oxide, Tin oxide, and Copper oxide

Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway

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