Mechanised wire-wise verification of Handel-C synthesis

Perna, Juan Ignacio; Woodcock, Jim

doi:10.1016/j.scico.2010.02.007

Cited by 4 publications

(1 citation statement)

References 5 publications

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“…This synthesis back end can seamlessly integrate with the proof-producing HOL4 to Verilog translator as it is based on the same Verilog semantics, and therefore creates verified translation from HOL4 circuit descriptions to synthesised Verilog netlists. Perna et al designed a formally verified translator from a deep embedding of Handel-C [Aubury et al 1996] into a deep embedding of a circuit [Perna and Woodcock 2012;Perna et al 2011]. Finally, Ellis [2008] used Isabelle to implement and reason about intermediate languages for software/hardware compilation, where parts could be implemented in hardware and the correctness could still be shown.…”

Section: Usable Toolmentioning

confidence: 99%

Formal verification of high-level synthesis

Herklotz

Pollard

Ramanathan

et al. 2021

Proc. ACM Program. Lang.

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High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any reasoning conducted at the software level. Furthermore, there is mounting evidence that existing HLS tools are quite unreliable, sometimes generating wrong hardware or crashing when given valid inputs. To address this problem, we present the first HLS tool that is mechanically verified to preserve the behaviour of its input software. Our tool, called Vericert, extends the CompCert verified C compiler with a new hardware-oriented intermediate language and a Verilog back end, and has been proven correct in Coq. Vericert supports most C constructs, including all integer operations, function calls, local arrays, structs, unions, and general control-flow statements. An evaluation on the PolyBench/C benchmark suite indicates that Vericert generates hardware that is around an order of magnitude slower (only around 2× slower in the absence of division) and about the same size as hardware generated by an existing, optimising (but unverified) HLS tool.

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Section: Usable Toolmentioning

confidence: 99%

Formal verification of high-level synthesis

Herklotz

Pollard

Ramanathan

et al. 2021

Proc. ACM Program. Lang.

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Contracts in CML

Woodcock

Cavalcanti

Fitzgerald

et al. 2014

Lecture Notes in Computer Science

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We describe the COMPASS Modelling Language (CML), which is used to model large-scale Systems of Systems and the contracts that bind them together. The language can be used to document the interfaces to constituent systems using formal, precise, and veriable specications including preconditions, postconditions, and invariants. The semantics of CML directly supports the use of these contracts for all language constructs, including the use of communication channels, parallel processes, and processes that run forever. Every process construct in CML has an associated contract, allowing clients and suppliers to check that the implementations of constituent systems conform to their interface specications.

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An Empirical Study of the Reliability of High-Level Synthesis Tools

Herklotz

Ramanathan

et al. 2021

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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Mechanised wire-wise verification of Handel-C synthesis

Cited by 4 publications

References 5 publications

Formal verification of high-level synthesis

Formal verification of high-level synthesis

Contracts in CML

An Empirical Study of the Reliability of High-Level Synthesis Tools

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