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Increasing the bit density in 3D NAND flash memory involves reducing the pitch of ON (Oxide-Nitride) molds in the Z-direction. However, this reduction drastically increases Z-interference, adversely affecting cell distribution and accelerating degradation of reliability limits. Previous studies have shown that programming from the top word line (WL) to the bottom WL, instead of the traditional bottom-to-top approach, alleviates Z-interference. Nevertheless, detailed analysis of how Z-interference varies at each WL depending on the programming sequence remains insufficient. This paper investigates the causes of Z-interference variations at Top, Middle, and Bottom WLs through TCAD analysis. It was found that as more electrons are programmed into WLs within the string, Z-interference variations increase due to increased resistance in the poly-Si channel. These variations are exacerbated by tapered vertical channel profiles resulting from high aspect ratio etching. To address these issues, a method is proposed to adjust bitline biases during verification operations of each WL. This method has been validated to enhance the performance and reliability of 3D NAND flash memory.
Increasing the bit density in 3D NAND flash memory involves reducing the pitch of ON (Oxide-Nitride) molds in the Z-direction. However, this reduction drastically increases Z-interference, adversely affecting cell distribution and accelerating degradation of reliability limits. Previous studies have shown that programming from the top word line (WL) to the bottom WL, instead of the traditional bottom-to-top approach, alleviates Z-interference. Nevertheless, detailed analysis of how Z-interference varies at each WL depending on the programming sequence remains insufficient. This paper investigates the causes of Z-interference variations at Top, Middle, and Bottom WLs through TCAD analysis. It was found that as more electrons are programmed into WLs within the string, Z-interference variations increase due to increased resistance in the poly-Si channel. These variations are exacerbated by tapered vertical channel profiles resulting from high aspect ratio etching. To address these issues, a method is proposed to adjust bitline biases during verification operations of each WL. This method has been validated to enhance the performance and reliability of 3D NAND flash memory.
Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values.
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