Measuring the effects of thread placement on the Kendall Square KSR1

Abstract

This paper describes a meuurement study of the effects of thread placement on memory access times on the Kendall Squ_re multiprocessor, the KSRI. The KSRI uses a conventions] shared memory prograunming mode] in a d_stributed memory axchitecture. The &rchitecture is b_ed on a ring of rings of 64-bit superscalar microprocessors. The KSRI has a Cache-Only Memory Architecture (COMA). Memory consists of the local cache memories attached to each processor. Whenever an address is accessed, the data item is automatically copied to the local cache memory module, so that access times for subsequent references will be minimal. If a local cache has space allocated for a paxticulsr data item, but does not have a current valid copy of that data item, then it is possible for the cache to acquire a valid read-only copy before it is requested by the local processor due to a request by a different processor that happens to pass by on the ring. This automatic prefetching can greatly reduce the averase time for a thread to acquire data items. Because of the automatic prefetching, the time required to obtain a valid copy of a data item does not depend simply on the distance from the owner of the data item, but s]so depends on the placement a_d number of other processing threads which sh_re the sa_nae data item. Al , the strategic placement of processing threads helps programs t_ke advantage of the unique features of the memory architecture which help eliminate memory access bottlenecks for shared data sets. Experiments run on the KSRI across a wide v_riety of thread configurations show that shared memory access is _ccelerated through stratesic placement of threads which sha_e data. The results indicate strategies for improving the performance of applications programs, and illustrate that KSRI memory access times can remain nearly constant even when the number of participating threads increases.

A Metric for the Temporal Characterization of Parallel Programs

“…We have observed that reads leading to coherence misses on write-invalidate architectures (interprocess reads) occur in bursts in simple programs like sort and complex application programs like the Splash benchmarks [12]. We also have verified the suggestion of [15] and [9] that programs with identical average read sharing characteristics can vary significantly in execution time due to differences in sharing at small time scales. This work involved a cache-only memory architecture that included a form of cache update called read-broadcast.…”

Latency hiding on COMA multiprocessors

“…Wagner et al [7] studied the impact of thread placement on performance using a set of synthetic benchmarks. They conducted experiments on a two-ring 64-processor system.…”