Measuring the effectiveness of ISO26262 compliant self test library

Pratas, Frederico; Dedes, Thomas; Webber, Andrew Lloyd; Bemanian, Majid; Yarom, Itai

doi:10.1109/isqed.2018.8357281

Cited by 9 publications

(3 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In other cases users resort to functional solutions, e.g. based on the so-called Self-Test Libraries [38], which rely on the Software-based Self-test approach [39], [40]. This solution seems particularly effective for in-field test of complex systems, since it allows to exploit self-test code provided by the developer of the modules composing the system and able to achieve a given fault coverage, which is integrated by the user into the application code and run when required to achieve the target reliability figures (e.g., at the Power-On, or periodically, or when specific error conditions happen).…”

Section: Reliability Enhancementmentioning

confidence: 99%

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

Jenihhin

Reorda

Balakrishnan

et al. 2019

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

View full text Add to dashboard Cite

The gigantic complexity and heterogeneity of today's advanced cyber-physical systems and systems of systems is multiplied by the use of avant-garde computing architectures to employ artificial intelligence based autonomy in the system. Here, the overall system's reliability comes along with requirements for fail-safe, fail-operational modes specific to the target applications of the autonomous system and adopted HW architectures. The paper makes an overview of reliability challenges for intelligence implementation in autonomous systems enabled by HW backbones such as neuromorphic architectures, approximate computing architectures, GPUs, tensor processing units (TPUs) and SoC FPGAs.

show abstract

Section: Reliability Enhancementmentioning

confidence: 99%

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

Jenihhin

Reorda

Balakrishnan

et al. 2019

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

View full text Add to dashboard Cite

show abstract

“…To reduce the impact of safety mechanisms on performance, we propose an approach that exploits the idle time of the CPU to execute test routines, i.e., Self-Test Libraries (STL). Well-established Functional Safety standards, such as ISO 26262, require high coverage of random hardware faults, for which STLs have been identified as an effective safety mechanism, providing high coverage without any impact on the device's design [5]. However, to achieve the target protection level STLs need to stimulate as much as possible the internal logic of the component, imposing a significant overhead on the nominal execution [6].…”

Section: Introductionmentioning

confidence: 99%

HUSTLE: A Hardware Unit for Self-test-Libraries Efficient Execution

Ferrante,

Terrosi,

Maruccio

et al. 2024

Lecture Notes in Electrical Engineering

View full text Add to dashboard Cite

Online testing of computer systems is crucial in contexts such as the safety-critical domain, where the software is usually made of functional code, which is the code implementing the application-specific functionalities, and nonfunctional code, which implements auxiliary functionalities, e.g., test routines. By periodically running a test routine it is possible to satisfy the high dependability requirements mandated by regulators, and defined in safety standards such as ISO26262, IEC61508, and CENELEC EN 5012X. Self-Test Libraries (STLs) are a form of software-based self-test, widely used in safety-related applications. The main drawback of this safety mechanism is the overhead imposed on the execution of the functional code, and reducing this overhead is a well-known challenge in research. We propose here HUSTLE, a Hardware Unit for STL Efficient execution, which can be integrated into the chip design with no modification to the CPU's internal logic. We also propose a scheduling mechanism that allows HUSTLE to efficiently execute self-tests, by exploiting the CPU's idle time. This is achieved by storing test code in a separate memory and sending instructions to the CPU, bypassing the Instruction Cache, thus allowing to reduce the overall execution time and the cache interference of STL, while CPU utilization increases.

show abstract

“…All the proposed solutions are based on the usage of commercially available EDA tools, thus being easily adoptable by professionals in the field. To the best of our knowledge, with respect to similar works [20], [21], this paper is the first attempt to provide a comprehensive and commented overview about the techniques that can be adopted to effectively perform the fault grading of STLs.…”

Section: Introductionmentioning

confidence: 99%

Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications

2019

View full text Add to dashboard Cite

The adoption of complex and technologically advanced integrated circuits (ICs) in safetycritical applications (e.g., in automotive) forced the introduction of new solutions to guarantee the achievement of the required reliability targets. One of these solutions lies in performing in-field test (i.e., the test performed when the device is already deployed in the mission environment) to detect faults that may arise in this phase of electronic circuit life. In this scenario, one increasingly adopted approach is based on the software test libraries (STLs), i.e., suitable code which is run by the CPU included in the system and is able to detect the existence of possible permanent faults both in the CPU itself and in the rest of the system. In order to assess the effectiveness of the STLs, fault simulation is performed, so that the achieved fault coverage (e.g., in terms of stuck-at faults) can be computed. This paper explains why the fault simulation of the STLs represents a different problem with respect to the classical fault simulation of test stimuli (for which very effective algorithms and tools are available), shows why it can be highly computationally expensive, and overviews some solutions to reduce the computational cost and possibly trade-off between results accuracy and cost.

show abstract

Measuring the effectiveness of ISO26262 compliant self test library

Cited by 9 publications

References 5 publications

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

HUSTLE: A Hardware Unit for Self-test-Libraries Efficient Execution

Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications

Contact Info

Product

Resources

About