2020
DOI: 10.1088/1748-0221/15/06/p06023
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Measurements of Single Event Upset in ATLAS IBL

Abstract: A: Effects of Single Event Upsets (SEU) and Single Event Transients (SET) are studied in the FE-I4B chip of the innermost layer of the ATLAS pixel system. SEU/SET affect the FE-I4B Global Registers as well as the settings for the individual pixels, causing, among other things, occupancy losses, drops in the low voltage currents, noisy pixels, and silent pixels. Quantitative 1Corresponding author.

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Cited by 6 publications
(9 citation statements)
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“…In addition, the triple redundant architecture is adopted for the global memory. Even with these treatments, SEEs became visible in IBL in high luminosity condition after 2017 [20].…”
Section: Sees In Iblmentioning
confidence: 99%
See 1 more Smart Citation
“…In addition, the triple redundant architecture is adopted for the global memory. Even with these treatments, SEEs became visible in IBL in high luminosity condition after 2017 [20].…”
Section: Sees In Iblmentioning
confidence: 99%
“…8. The LV current consumption and hit occupancy for two IBL modules as a function of LB (left) and the noise occupancy in IBL modules as a function of integrated luminosity with and without mechanism to reconfigure the pixel cell memory (right) [20]. Although reconfiguration of the global memory is performed every five seconds in the normal operation, it is delayed to test the functionality in the left plot.…”
Section: Sees In Sctmentioning
confidence: 99%
“…(Right) Fraction of silent pixels due to SEU effects as a function of the integrated luminosity in LHC fill 7018 taken in 2018. Data are shown for the eight 3D IBL 𝜂 rings with and without pixel register reconfiguration (from [19]).…”
Section: Marco Battagliamentioning
confidence: 99%
“…Single Event Upset (SEU) and Single Event Transient (SET) affect the IBL FE global registers and the settings for individual pixels causing occupancy losses, noisy and silent pixels during data taking. SEU and SET effects have been studied in detail for the IBL FE-I4 chips [19]. Mitigation through reconfiguration of pixel registers during the LHC runs was tested in 2018 and the results are summarised in the right panel of Figure 3.…”
Section: Pos(pixel2022)006mentioning
confidence: 99%
“…The module was reconfigured five luminosity blocks later. The current and occupancy returned to To handle SEUs in the FE-I4 a mechanism to reconfigure the global registers was introduced during Run 2 [9]. This mechanism does not add any additional dead-time by exploiting the eventcounter-reset (ECR) signal.…”
Section: Pos(eps-hep2021)819mentioning
confidence: 99%