Measurements of gate voltage dependence of electron mobility in delta -doped HFET's

Moon, B.-J.; Lee, S.; Shur, M. S.; Morkoç̌, H.; Gopinath, A.

doi:10.1109/16.231581

Cited by 7 publications

(8 citation statements)

References 14 publications

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“…The enhanced surface roughness scattering at higher V gs regime leads to a decrease of μ eff , while Coulomb scattering due to fixed interface state charges and ionized impurity charges is responsible for the reduction of μ eff at negative V gs . , In addition, the μ eff − V g dependence is asymmetric with a fast roll-off at voltage close to the threshold voltage. This feature is also in accordance with the observations in GaAs thin film MOSFET, indicating the good subthreshold characteristics of the top-gate CdSe:In NWFET. From Figure d, the peak mobility reaches 166 cm 2 /(V·s) at V ds = 1 V and V gs = −0.1 V, which is the highest value reported thus far for CdSe nanomaterials , and films, , although it is still smaller than that reported for single-crystal CdSe and Si NWFET devices (350 cm 2 /(V·s)) .…”

Section: Resultssupporting

confidence: 90%

“…35,36 In addition, the µ eff -V g dependence is asymmetric with a fast roll-off at voltage close to the threshold voltage. This feature is also in accordance with the observations in GaAs thin film MOSFET, 37 indicating the good subthreshold characteristics of the top-gate CdSe:In NWFET. From Figure 3d, the peak mobility reaches 166 cm 2 /(V • s) at V ds ) 1 V and V gs ) -0.1 V, which is the highest value reported thus far for CdSe nanomaterials 27,28 and films, 38,39 although it is still smaller than that reported for single-crystal CdSe 32 and Si NWFET devices (350 cm 2 /(V • s)).…”

Section: Resultssupporting

confidence: 90%

See 1 more Smart Citation

High-Performance CdSe:In Nanowire Field-Effect Transistors Based on Top-Gate Configuration with High-κ Non-Oxide Dielectrics

He¹,

Zhang²,

Zhang³

et al. 2010

J. Phys. Chem. C

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A dual-gate field-effect transistor (FET) based on the same single indium-doped CdSe nanowire using Si3N4 and SiO2 as top- and back-gate dielectrics, respectively, was fabricated. This dual-gate FET enabled direct comparison of the device performance of FETs in both top- and back-gate configurations. Remarkably, the field-effect mobility, peak transconductance, and I on/I off ratio of the Si3N4 top-gate FET were 52, 142, and 2.81 × 105 times larger than the respective values of the SiO2 back-gate FET. Meanwhile, the threshold voltage and the subthreshold swing of the top-gate FET decreased to −1.7 V and 508 mV/decade, respectively, which are better than the best values ever obtained in FETs based on II−VI semiconductor nanomaterials including CdSe nanowires. The roles of device configurations and gate materials in the FET characteristics and the evaluation of electronic and transport properties of nanostructures based on that were discussed. Two kinds of basic logic circuits, “AND” and “OR”, were constructed with the top-gate transistors, which could also utilize light-input to realize a phototransistor action to take advantage of its photoresponse properties.

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Section: Resultssupporting

confidence: 90%

Section: Resultssupporting

confidence: 90%

High-Performance CdSe:In Nanowire Field-Effect Transistors Based on Top-Gate Configuration with High-κ Non-Oxide Dielectrics

He¹,

Zhang²,

Zhang³

et al. 2010

J. Phys. Chem. C

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“…Here, g m is the intrinsic transconductance, V DS is the voltage drop across L G , and C is the gate capacitance, which is equal to the oxide capacitance in the linear regime. , Note that at both positive and negative gate voltages, the field-effect mobility is low and increases as V GS approaches the flat band voltage, V fb , which is typically less than 0 V due to the presence of positively charged donor-type surface states that shift V fb to negative values. The μ FE − V GS dependence shown in Figure a follows the same trends as those observed in metal-oxide-semiconductor FETs and heterojunction FETs . For positive voltages in the accumulation regime, μ FE decreases due to surface roughness scattering. , For negative gate voltages below V fb in the depletion regime, Coulomb scattering due to fixed oxide charges, interface state charges, and ionized impurity charges reduces μ FE .…”

supporting

confidence: 63%

“…Coulomb scattering is dominant at low carrier densities and is reduced at higher densities due to screening of the charged centers’ potential. The μ FE − V GS dependence is typically asymmetric, with fast roll-off at voltages close to the threshold voltage. , For the InAs NWFETs, however, the large surface state density leads to poor subthreshold characteristics and to the more symmetric appearance of the μ FE − V GS curve as shown in Figure a.…”

mentioning

confidence: 98%

Field Dependent Transport Properties in InAs Nanowire Field Effect Transistors

et al. 2008

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We present detailed studies of the field dependent transport properties of InAs nanowire field-effect transistors. Transconductance dependence on both vertical and lateral fields is discussed. Velocity-field plots are constructed from a large set of output and transfer curves that show negative differential conductance behavior and marked mobility degradation at high injection fields. Two dimensional electrothermal simulations at current densities similar to those measured in the InAs NWFET devices indicate that a significant temperature rise occurs in the channel due to enhanced phonon scattering that leads to the observed mobility degradation. Scanning transmission electron microscopy measurements on devices operated at high current densities reveal arsenic vaporization and crystal deformation in the subject nanowires.

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“…As the gate voltage approaches the flat-band voltage (typically negative due to donor surface charges), the mobility peaks, and then reduces as V GS increases in the accumulation region near the surface due to interface roughness scattering [64,65]. The symmetric behavior of μ FE -V GS observed here is due to the poor sub-threshold characteristics (non-steep turn-on characteristics) of the InAs NWFETs and should be typically more steep in the absence of surface states for voltages below the flat-band voltage [64,66].…”

Section: Field Dependencementioning

confidence: 69%

Electron transport in indium arsenide nanowires

Dayeh

2010

Semicond. Sci. Technol.

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The vapor-liquid-solid growth of semiconductor nanowires led to the implementation of engineered electronic and optoelectronic one-dimensional nanostructures with outstanding promise for device applications. To realize this promise, detailed understanding and control over their growth, crystal structure, and transport properties and their combined impact on device performance is vital. Here, we review our work on electron transport in InAs nanowires in a variety of device schemes. First, we provide a brief introduction and historical perspective on growth and transport studies in InAs NWs. Second, we discuss and present experimental measurements of ballistic transport in InAs nanowires over ∼200 nm length scale, which indicates a large electron mean free path and correlates with the high electron mobility measured on similar nanowires. Third, we devise a device model that enables accurate estimation of transport coefficients from field-effect transistor measurements by taking into account patristic device components. We utilize this model to reveal the impact of surface states, diameter, lateral and vertical fields, as well as crystal structure, on electron transport and transport coefficient calculation. We show in these studies that electron transport in InAs nanowires is dominated by surface state effects that introduce measurement artifacts in parameter extraction, reduce electron mobility for smaller diameters, and degrade the subthreshold characteristics of transistors made of Zinc Blende InAs nanowires. This device model is also used for isolating vertical and lateral field effects on electron transport in nanowire transistor channels and explaining observed negative differential conductance and mobility degradation at high injection fields, which is supported by electro-thermal simulations and microstructure failure analysis. We adopt the concept of lack of inversion symmetry in polar III-V materials and the resultant spontaneous polarization charges perpendicular to the electron transport trajectory in twinned Wurtzite nanowires to explain compensation of surface charges for this type of nanowires and their enhanced subthreshold characteristics over transistors made of Zinc Blende ones. Fourth, we discuss the combined effects of surface states and field variations in InAs nanowire transistor channels to shed light on the local electrostatic behavior in 1D channels studied by scanning probe measurements. Fifth, we survey and benchmark results on nanowire transistor performance and demonstrate the superiority of InAs nanowires for high-on currents and high-speed applications. Finally, we implement a novel integration scheme for InAs nanowires on Si substrates that enables vertical alignment and electrical isolation between nanowires which is necessary for achieving multifunctional devices per single chip.

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Measurements of gate voltage dependence of electron mobility in delta -doped HFET's

Cited by 7 publications

References 14 publications

High-Performance CdSe:In Nanowire Field-Effect Transistors Based on Top-Gate Configuration with High-κ Non-Oxide Dielectrics

High-Performance CdSe:In Nanowire Field-Effect Transistors Based on Top-Gate Configuration with High-κ Non-Oxide Dielectrics

Field Dependent Transport Properties in InAs Nanowire Field Effect Transistors

Electron transport in indium arsenide nanowires

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