Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection

Schenkel, Michael; Pfäffli, Paul; Mettler, S.; Reiner, W.; Aemmer, W.D.

doi:10.1109/essderc.2000.194849

Cited by 13 publications

(4 citation statements)

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“…In circuit implementations, this may e.g. forward bias parasitic diodes which in turn may inject current into the substrate, yields significant gradients in the substrate potential across the chip and yielding latch up risks that may destroy the PA operation [33], [34] when improperly handled. Circuit solutions such as used in e.g.…”

Section: And ω0mentioning

confidence: 99%

Load Mismatch Sensitivity of Class-E Power Amplifiers

Ghahremani

Annema

Nauta

2019

IEEE Trans. Microwave Theory Techn.

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Class-E RF Power Amplifiers (PAs) are very power efficient under nominal operating conditions. Due to incorporating two tuned tanks, the dependency on the load impedance is however relatively large, resulting in e.g. load dependent output power, power efficiency, peak voltages and peak (and average) currents which can lead to reliability issues. This paper presents load-pull analyses for class-E RF power amplifiers from a mathematical perspective, with analyses and discussions of the effects of the most common non-idealities of class-E PAs: the limited loaded quality factor (Q loaded) of the series filter, switch on-resistance, limited quality factor of the dc-feed inductor, loadmismatch dependent switch conduction loss and the limited negative voltage excursions (due to e.g. the reverse conduction of the switch transistor for negative voltage excursions). The theoretical findings are backed up by extensive circuit simulations and loadpull measurements of a class-E power amplifier implemented in 65 nm CMOS technology. The PA provides 18.1 dBm output power and 72% efficiency at 1.4 GHz under nominal operating condition employing an off-chip matching network.

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Section: And ω0mentioning

confidence: 99%

Load Mismatch Sensitivity of Class-E Power Amplifiers

Ghahremani

Annema

Nauta

2019

IEEE Trans. Microwave Theory Techn.

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“…On the other hand, minority and majority carrier lifetimes need to be considered and well adjusted in recombination model. These carrier lifetimes can be adjusted by calibrating parasitic BJT gain measurement and simulation [5].…”

Section: Model Calibrationmentioning

confidence: 99%

ESD simulation on GGNMOS for 40V BCD

Herlambang

Sheu

Yang

et al. 2010

TENCON 2010 - 2010 IEEE Region 10 Conference

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In this paper, TCAD was used to simulate GGNMOS (Grounded-Gate NMOS) as an ESD protection device for 40V BCD. The physic models and the calibration method are discussed in order to get better accuracy on the result. The effects of device parameter on the ESD robustness are investigated by device simulation in order to achieve the desired ESD design window. The simulated holding voltage is in agreement with BJT model that already proven has an agreement with silicon result. Finally, the ESD design window for 40V BCD device can be obtained by changing some device parameters.

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“…In normal operating conditions power stages are switching and electrons and holes are injected in the substrate resulting in parasitic currents or local potential shift that can reach several millivolts [2]. This leads to unwanted parasitic couplings that can seriously compromise sensitive low voltage circuits on the surroundings.…”

Section: Introductionmentioning

confidence: 99%

Optimization strategy of numerical simulations applied to EPFL substrate model

Stefanucci

Buccella

Kayal

et al. 2014

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)

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A new methodology for modeling minority carriers diffusion in Smart Power ICs substrate using standard circuit simulators has been proposed by EPFL. For this purpose, a parasitic substrate network consisting of lumped elements is extracted from the circuit layout following a given substrate meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the influence of the meshing on the accuracy of the EPFL Substrate Model when compared to finite element simulations. A two-dimensional case study on a parasitic lateral bipolar is then proposed with both spice-like and finite element simulation results for the minority carriers diffusion. A linear model is developed to estimate the most important geometrical domains influencing the accuracy of the studied model.

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Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection

Cited by 13 publications

References 0 publications

Load Mismatch Sensitivity of Class-E Power Amplifiers

Load Mismatch Sensitivity of Class-E Power Amplifiers

ESD simulation on GGNMOS for 40V BCD

Optimization strategy of numerical simulations applied to EPFL substrate model

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